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Message-ID: <CALCETrX0D3pM29VCve68nvZNQEYNXNMp90HZes5CMoWWs0t7AA@mail.gmail.com>
Date:	Mon, 26 Oct 2015 19:56:06 -0700
From:	Andy Lutomirski <luto@...capital.net>
To:	Borislav Petkov <bp@...en8.de>
Cc:	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...nel.org>,
	"H. Peter Anvin" <hpa@...or.com>,
	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>,
	Tony Luck <tony.luck@...el.com>, X86 ML <x86@...nel.org>,
	ashok.raj@...el.com,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	linux-edac <linux-edac@...r.kernel.org>,
	Peter Zijlstra <peterz@...radead.org>,
	Andrew Lutomirski <luto@...nel.org>,
	Denys Vlasenko <dvlasenk@...hat.com>,
	Ross Zwisler <ross.zwisler@...ux.intel.com>,
	Dirk Brandewie <dirk.j.brandewie@...el.com>,
	Wan Zongshun <Vincent.Wan@....com>
Subject: Re: [RFC PATCH] x86/cpu: Move sparsely used bit leafs into scattered
 features (was: Re: [PATCH 2/2] x86/cpufeature: Add CLZERO feature)

On Mon, Oct 26, 2015 at 2:01 PM, Borislav Petkov <bp@...en8.de> wrote:
> On Mon, Oct 26, 2015 at 09:22:50PM +0100, Borislav Petkov wrote:
>> And btw, those Intel QoS single bit defines and the XSAVE stuff there
>> should move to that function too - that's a pure waste having them in
>> the cap_flags array. I'll fix that.
>
> I.e., something like that (I'm jetlagged and I can't sleep, bah :-\).
>
> So this one builds but no further guarantees. It looks straightforward
> though.
>
> Not-yet-signed-off-by: Borislav Petkov <bp@...e.de>
>
> ---
> diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
> index 9727b3b48bd1..ea109b58a864 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -12,7 +12,7 @@
>  #include <asm/disabled-features.h>
>  #endif
>
> -#define NCAPINTS       13      /* N 32-bit words worth of info */
> +#define NCAPINTS       10      /* N 32-bit words worth of info */
>  #define NBUGINTS       1       /* N 32-bit bug flags */
>
>  /*
> @@ -198,6 +198,15 @@
>  #define X86_FEATURE_HWP_EPP    ( 7*32+13) /* Intel HWP_EPP */
>  #define X86_FEATURE_HWP_PKG_REQ ( 7*32+14) /* Intel HWP_PKG_REQ */
>  #define X86_FEATURE_INTEL_PT   ( 7*32+15) /* Intel Processor Trace */
> +/* Extended state features, CPUID level 0x0000000d:1 (eax) */
> +#define X86_FEATURE_XSAVEOPT   (7*32+ 16) /* XSAVEOPT */
> +#define X86_FEATURE_XSAVEC     (7*32+ 17) /* XSAVEC */
> +#define X86_FEATURE_XGETBV1    (7*32+ 18) /* XGETBV with ECX = 1 */
> +#define X86_FEATURE_XSAVES     (7*32+ 19) /* XSAVES/XRSTORS */

How few features in one leaf do we need before calling it scattered
makes sense?  These four might make sense to keep as is...

> +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx) */
> +#define X86_FEATURE_CQM_LLC    (7*32+ 20) /* LLC QoS if 1 */
> +/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx) */
> +#define X86_FEATURE_CQM_OCCUP_LLC (7*32+ 21) /* LLC occupancy monitoring if 1 */
>

...whereas this looks totally reasonable.

FWIW, we have a ton of thses things.  Would it make sense to convert
this to a text file giving features and their CPUID positions that
generates the defines and the code to enumerate them?

--Andy
--
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