linux-kernel - Re: [PATCH 0/2] "big hammer" for DAX msync/fsync correctness

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Message-ID: <20151028225112.GA30284@linux.intel.com>
Date:	Wed, 28 Oct 2015 16:51:12 -0600
From:	Ross Zwisler <ross.zwisler@...ux.intel.com>
To:	Jeff Moyer <jmoyer@...hat.com>
Cc:	Ross Zwisler <ross.zwisler@...ux.intel.com>,
	linux-kernel@...r.kernel.org, linux-nvdimm@...1.01.org,
	Dave Chinner <david@...morbit.com>, x86@...nel.org,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>, Jan Kara <jack@...e.com>
Subject: Re: [PATCH 0/2] "big hammer" for DAX msync/fsync correctness

On Wed, Oct 28, 2015 at 06:24:29PM -0400, Jeff Moyer wrote:
> Ross Zwisler <ross.zwisler@...ux.intel.com> writes:
> 
> > This series implements the very slow but correct handling for
> > blkdev_issue_flush() with DAX mappings, as discussed here:
> >
> > https://lkml.org/lkml/2015/10/26/116
> >
> > I don't think that we can actually do the
> >
> >     on_each_cpu(sync_cache, ...);
> >
> > ...where sync_cache is something like:
> >
> >     cache_disable();
> >     wbinvd();
> >     pcommit();
> >     cache_enable();
> >
> > solution as proposed by Dan because WBINVD + PCOMMIT doesn't guarantee that
> > your writes actually make it durably onto the DIMMs.  I believe you really do
> > need to loop through the cache lines, flush them with CLWB, then fence and
> > PCOMMIT.
> 
> *blink*
> *blink*
> 
> So much for not violating the principal of least surprise.  I suppose
> you've asked the hardware folks, and they've sent you down this path?

Sadly, yes, this was the guidance from the hardware folks.
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