lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <alpine.DEB.2.10.1510280621470.2865@atull-730U3E-740U3E>
Date:	Wed, 28 Oct 2015 06:41:04 -0600
From:	atull <atull@...nsource.altera.com>
To:	Josh Cartwright <joshc@...com>
CC:	<gregkh@...uxfoundation.org>,
	Moritz Fischer <moritz.fischer@...us.com>, <monstr@...str.eu>,
	<michal.simek@...inx.com>, Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	"Kumar Gala" <galak@...eaurora.org>,
	Jonathan Corbet <corbet@....net>,
	<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
	<linux-doc@...r.kernel.org>, <pantelis.antoniou@...sulko.com>,
	<delicious.quinoa@...il.com>, <dinguyen@...nsource.altera.com>
Subject: Re: [PATCH v12 3/6] fpga: add simple-fpga-bus

On Wed, 28 Oct 2015, Josh Cartwright wrote:

> On Tue, Oct 27, 2015 at 05:09:12PM -0500, atull@...nsource.altera.com wrote:
> > From: Alan Tull <atull@...nsource.altera.com>
> > 
> > The Simple FPGA bus uses the FPGA Manager Framework and the
> > FPGA Bridge Framework to provide a manufactorer-agnostic
> > interface for reprogramming FPGAs that is Device Tree
> > Overlays-based.
> 
> Do you intend the "simple-fpga-bus" to be used on Zynq as well?

Yes

>  The
> whole concept of the socfpga's "FPGA Bridge" doesn't map to the Zynq at
> all, from what I can tell.

I want to make this useful for all of us.  I'll make some minor changes so
the simple fpga bus will not exit when it encounters an overlay that doesn't
specify any bridges.

Zynq doesn't have bridges to disable during reconfiguration?  I guess
that's handled automatically in hardware somehow?

> 
> Therefore, I would have expected the FPGA Bridge drivers to sit under
> the fpga-socfpga driver, and not be a first class feature of the
> kernels' FPGA manager subsystem.

I need some way for simple FPGA bus to be able to configure bridges during
the reconfiguration cycle.  That will have to hook into the simple fpga bus,
even if not everybody uses it.  I'll submit minor changes that make it
convenient to either have bridges if you need them or leave them out if
you don't.

Alan

> 
>   Josh
> 


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ