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Message-ID: <1446059010-28010-3-git-send-email-Aravind.Gopalakrishnan@amd.com>
Date: Wed, 28 Oct 2015 14:03:30 -0500
From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
To: <tglx@...utronix.de>, <mingo@...hat.com>, <hpa@...or.com>,
<tony.luck@...el.com>, <bp@...en8.de>, <x86@...nel.org>
CC: <ashok.raj@...el.com>, <linux-kernel@...r.kernel.org>,
<linux-edac@...r.kernel.org>, <peterz@...radead.org>,
<luto@...nel.org>, <dvlasenk@...hat.com>,
<ross.zwisler@...ux.intel.com>, <dirk.j.brandewie@...el.com>,
Wan Zongshun <Vincent.Wan@....com>,
"Aravind Gopalakrishnan" <aravind.gopalakrishnan@....com>
Subject: [PATCH V2 2/2] x86/cpufeature: Add CLZERO feature
From: Wan Zongshun <Vincent.Wan@....com>
CLZERO instruction introduced in AMD Fam17h processors
zero's out a 64 byte cache line specified in RAX.
Add the bit here to allow /proc/cpuinfo to list the feature
Signed-off-by: Wan Zongshun <Vincent.Wan@....com>
[Wrap code in patch form, fix comments]
Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
---
arch/x86/include/asm/cpufeature.h | 5 ++++-
arch/x86/kernel/cpu/common.c | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 9727b3b..e4f8010 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -12,7 +12,7 @@
#include <asm/disabled-features.h>
#endif
-#define NCAPINTS 13 /* N 32-bit words worth of info */
+#define NCAPINTS 14 /* N 32-bit words worth of info */
#define NBUGINTS 1 /* N 32-bit bug flags */
/*
@@ -255,6 +255,9 @@
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
+/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
+#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
+
/*
* BUG word(s)
*/
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index de22ea7..4ddd780 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -670,6 +670,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_virt_bits = (eax >> 8) & 0xff;
c->x86_phys_bits = eax & 0xff;
+ c->x86_capability[13] = cpuid_ebx(0x80000008);
}
#ifdef CONFIG_X86_32
else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
--
2.6.1
--
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