linux-kernel - Re: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

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Message-ID: <20151029182801.GA7007@chopperman.am.freescale.net>
Date:	Thu, 29 Oct 2015 13:28:03 -0500
From:	Han Xu <han.xu@...escale.com>
To:	Bean Huo 霍斌斌 (beanhuo) 
	<beanhuo@...ron.com>
CC:	"b45815@...escale.com" <b45815@...escale.com>,
	"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
	"shijie.huang@....com" <shijie.huang@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"vinod.koul@...el.com" <vinod.koul@...el.com>,
	Boris Brezillon <boris.brezillon@...e-electrons.com>,
	Brian Norris <computersforpeace@...il.com>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>
Subject: Re: [PATCH v7 4/7] mtd: nand: gpmi: may use minimum required ecc

On Thu, Oct 29, 2015 at 04:34:37AM +0000, Bean Huo 霍斌斌 (beanhuo) wrote:
> > > > By default NAND driver will choose the highest ecc strength that oob
> > > > could contain, in this case, for some 8K+744 NAND flash, the ecc
> > > > strength will be up to 52bit, which beyonds the i.MX6QDL BCH capability
> > (40bit).
> > >
> > >
> > > For normal working environment, if hardware BCH ECC cannot meet NAND
> > > ecc requirement, We can set a minimum required ecc strength, and file
> > system refresh/scrub can control bitflips under NAND ecc strength. But during
> > reflow solder, it is very possible that NAND bitflips may increase over your
> > hardware BCH capability, I don't know how this controller handle this?
> > > For example, NAND require 80bit ECC, but hardware BCH ECC can only hold
> > 40bit.
> > > After reflow, there are some blocks that bitflips over 40bit.
> > 
> > if the minimum ecc strength read from NAND ONFI parameter exceeds the
> > BCH ECC capability, the NAND driver quits and reports unsupport NAND chip.
> 
> Current Linux already set ECC strength according to NAND minimum required ECC that read
> from ONFI table. So if NAND minimum required ECC is 60bit, but this BCH controller can only hold 40bit,
> NAND driver quits? Why not transfer to use software BCH ECC? 

SW ECC brings huge computational complexity, that's why needs HW ECC. I
think user should choose the proper NAND chip according to platfrom
capability rather than involve SW ECC in driver.

> 
> > Do you mean reflow solder may change the NAND minimum required ECC
> > strength, in other word, the actual minimum ECC may larger than it said in
> > NAND chip SPEC?
> 
> NAND minimum required ECC does not changed because of reflow.
> I mean that if hardware BCH ECC Can not meet nand minimum required ECC, during normal working, we can set
> ECC strength according to Your hardware ECC capability. 
> for example in this case, NAND minimum required ECC is 60bit, but hardware ECC capability Is 40bit, during normal working,
> we can set ECC strength according to 40bit, this can work, it will definitely increase PE cycle.
> But for reflow operation, there are some blocks that their bitflips will increase over your hardware ECC 40bit, so how do you handle this?
> Or you don't meet this case?

I don't quite understand, why 60bit ECC NAND can work on 40bit ECC
platform, it is quite possible to get uncorrectable ECC error. Excuse
me, I didn't get your point about reflow operation part, in your case,
the original ECC read from ONFI table has already beyond the HW ECC,
even without reflow.

> 
> 
> 
> > --
> > Best Regards,
> > 
> > Han "Allen" Xu
> 

-- 
Best Regards,

Han "Allen" Xu

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