linux-kernel - Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from master device node

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Message-ID: <87wpu5ifn2.fsf@belgarion.home>
Date:	Thu, 29 Oct 2015 21:28:01 +0100
From:	Robert Jarzmik <robert.jarzmik@...e.fr>
To:	Boris Brezillon <boris.brezillon@...e-electrons.com>
Cc:	Marek Vasut <marex@...x.de>,
	Brian Norris <computersforpeace@...il.com>,
	linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
	Ezequiel Garcia <ezequiel.garcia@...e-electrons.com>,
	Scott Wood <scottwood@...escale.com>,
	Josh Wu <josh.wu@...el.com>,
	Kyungmin Park <kyungmin.park@...sung.com>,
	Han Xu <han.xu@...escale.com>,
	Huang Shijie <shijie.huang@....com>
Subject: Re: [PATCH 1/5] mtd: ofpart: grab device tree node directly from master device node

Boris Brezillon <boris.brezillon@...e-electrons.com> writes:

> On Thu, 29 Oct 2015 18:23:47 +0100
> Marek Vasut <marex@...x.de> wrote:
> Except it's now how devices supporting 16 bits data bus are supposed to
> work, which means your NAND controller will probably not be able to
> send the command/address value on the higher 8 bits...
Correct.

>> > 2/ NAND chips can have bad blocks, so even if you were able to address
>> > 2 chips (which according to #1 is impossible), you might try to write
>> > on a bad block on the chip connected on the MSB side of the data bus.
>> 
>> This one is a valid problem. The other valid issue here is where the
>> command might fail on one chip and pass on the other.
Probably the bad block wins, and the command is reported as a failure.

>> > 3/ There probably are plenty of other reasons why this is not
>> > possible ;-).
>> 
>> It's possible, implementable, but a really bad idea.
>
> Possible and implementable, maybe with an adapted software stack
> and a customized NAND controller. I know you're working on emulating
> flash devices using FPGA, so the next step is to create a new NAND
> controller IP supporting that kind of stuff and adding support for
> this feature to the NAND framework ;-).
> Anyway, it"s definitely a bad idea.
I agree, a bad idea.

Just to finish the discussion, let me quote the pxa3xx developper manual volume
2, chapter 3.7.6.1 "Flash Memory Data Width when Two Flash Devices Connect to
the Same Chip" :
    When NDCR[DWIDTH_C] = 1 and NDCR[DWIDTH_M] = 0, two flash devices are
    connected to the same chip select with DF_IO<7:0> interfacing to one device,
    and DF_IO<15:8> interfacing to the second device. In this scenario, since
    two devices are accessed simultaneously, the command and address are
    replicated between the lower and upper byte of the interface.

Now, regardless of this, please continue with your patches, this corner case is
not important, at least I don't care at all.

Cheers.

-- 
Robert
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