linux-kernel - Re: [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor clock name from devicetree

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Date:	Fri, 30 Oct 2015 15:46:29 +0800
From:	Chen-Yu Tsai <wens@...e.org>
To:	Jens Kuske <jenskuske@...il.com>
Cc:	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Chen-Yu Tsai <wens@...e.org>,
	Michael Turquette <mturquette@...libre.com>,
	Linus Walleij <linus.walleij@...aro.org>,
	Rob Herring <robh+dt@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Emilio López <emilio@...pez.com.ar>,
	Vishnu Patekar <vishnupatekar0510@...il.com>,
	Hans de Goede <hdegoede@...hat.com>,
	devicetree <devicetree@...r.kernel.org>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	linux-kernel <linux-kernel@...r.kernel.org>,
	linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [PATCH v4 1/6] clk: sunxi: Let divs clocks read the base factor
 clock name from devicetree

On Wed, Oct 28, 2015 at 12:50 AM, Jens Kuske <jenskuske@...il.com> wrote:
> Currently, the sunxi clock driver gets the name for the base factor clock
> of divs clocks from the name field in factors_data. This prevents reusing
> of the factor clock for clocks with same properties, but different name.
>
> This commit makes the divs setup function try to get a name from
> clock-output-names in the devicetree. It also removes the name field where
> possible and merges the sun4i PLL5 and PLL6 clocks.

This patch actually removes all static declarations of the name field,
which is a good thing!

>
> Signed-off-by: Jens Kuske <jenskuske@...il.com>
> ---
>  drivers/clk/sunxi/clk-sunxi.c | 38 +++++++++++++++++++++++++++-----------
>  1 file changed, 27 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 9c79af0c..270de42 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -704,21 +704,12 @@ static const struct factors_data sun4i_pll5_data __initconst = {
>         .enable = 31,
>         .table = &sun4i_pll5_config,
>         .getter = sun4i_get_pll5_factors,
> -       .name = "pll5",
> -};
> -
> -static const struct factors_data sun4i_pll6_data __initconst = {
> -       .enable = 31,
> -       .table = &sun4i_pll5_config,
> -       .getter = sun4i_get_pll5_factors,
> -       .name = "pll6",
>  };
>
>  static const struct factors_data sun6i_a31_pll6_data __initconst = {
>         .enable = 31,
>         .table = &sun6i_a31_pll6_config,
>         .getter = sun6i_a31_get_pll6_factors,
> -       .name = "pll6x2",
>  };
>
>  static const struct factors_data sun5i_a13_ahb_data __initconst = {
> @@ -902,6 +893,7 @@ struct gates_data {
>
>  #define SUNXI_DIVS_MAX_QTY     4
>  #define SUNXI_DIVISOR_WIDTH    2
> +#define SUNXI_DIVS_BASE_NAME_MAX_LEN   8
>
>  struct divs_data {
>         const struct factors_data *factors; /* data for the factor clock */
> @@ -941,7 +933,7 @@ static const struct divs_data pll5_divs_data __initconst = {
>  };
>
>  static const struct divs_data pll6_divs_data __initconst = {
> -       .factors = &sun4i_pll6_data,
> +       .factors = &sun4i_pll5_data,
>         .ndivs = 4,
>         .div = {
>                 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
> @@ -983,6 +975,8 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
>         struct clk_gate *gate = NULL;
>         struct clk_fixed_factor *fix_factor;
>         struct clk_divider *divider;
> +       struct factors_data factors = *data->factors;
> +       char base_name[SUNXI_DIVS_BASE_NAME_MAX_LEN];
>         void __iomem *reg;
>         int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
>         int flags, clkflags;
> @@ -991,8 +985,30 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
>         if (data->ndivs)
>                 ndivs = data->ndivs;
>
> +       /* Try to find a name for base factor clock */
> +       for (i = 0; i < ndivs; i++) {
> +               if (data->div[i].self) {
> +                       of_property_read_string_index(node, "clock-output-names",
> +                                                     i, &factors.name);
> +                       break;
> +               }
> +       }
> +       /* If we don't have a .self clk use the first output-name up to '_' */

This actually only works for the sun4i divs clocks. sun6i-a31-pll6 uses a
different naming convention. sun4i-a10-pll2 uses yet another, though that's
not a divs clock. Maybe we should work on unifying them. Maxime?

Other than these 2 bits of information, this patch looks good.


Regards
ChenYu

> +       if (factors.name == NULL) {
> +               of_property_read_string_index(node, "clock-output-names",
> +                                                     0, &clk_name);
> +
> +               for (i = 0; i < SUNXI_DIVS_BASE_NAME_MAX_LEN - 1 &&
> +                                               clk_name[i] != '_' &&
> +                                               clk_name[i] != '\0'; i++)
> +                       base_name[i] = clk_name[i];
> +
> +               base_name[i] = '\0';
> +               factors.name = base_name;
> +       }
> +
>         /* Set up factor clock that we will be dividing */
> -       pclk = sunxi_factors_clk_setup(node, data->factors);
> +       pclk = sunxi_factors_clk_setup(node, &factors);
>         parent = __clk_get_name(pclk);
>
>         reg = of_iomap(node, 0);
> --
> 2.6.2
>
--
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