linux-kernel - [tip:ras/core] x86/mce: Add a Scalable MCA vendor flags bit

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Message-ID: <tip-c7f54d21fb02e90042e6233b46716dcb244e70e6@git.kernel.org>
Date:	Sun, 1 Nov 2015 02:27:50 -0800
From:	tip-bot for Aravind Gopalakrishnan <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	ashok.raj@...el.com, bp@...e.de, peterz@...radead.org,
	Aravind.Gopalakrishnan@....com, linux-kernel@...r.kernel.org,
	tony.luck@...el.com, torvalds@...ux-foundation.org,
	linux-edac@...r.kernel.org, hpa@...or.com, tglx@...utronix.de,
	mingo@...nel.org, bp@...en8.de
Subject: [tip:ras/core] x86/mce: Add a Scalable MCA vendor flags bit

Commit-ID:  c7f54d21fb02e90042e6233b46716dcb244e70e6
Gitweb:     http://git.kernel.org/tip/c7f54d21fb02e90042e6233b46716dcb244e70e6
Author:     Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
AuthorDate: Fri, 30 Oct 2015 13:11:37 +0100
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Sun, 1 Nov 2015 11:26:13 +0100

x86/mce: Add a Scalable MCA vendor flags bit

Scalable MCA (SMCA) is a new feature in AMD Fam17h processors
which indicates presence of MCA extensions.

MCA extensions expands existing register space for the MCE banks
and also introduces a new MSR range to accommodate new banks.

Add the detection bit.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
[ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ]
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: Ashok Raj <ashok.raj@...el.com>
Cc: Borislav Petkov <bp@...en8.de>
Cc: H. Peter Anvin <hpa@...or.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Tony Luck <tony.luck@...el.com>
Cc: linux-edac <linux-edac@...r.kernel.org>
Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/include/asm/mce.h       | 34 +++++++++++++++++++++-------------
 arch/x86/kernel/cpu/mcheck/mce.c |  2 ++
 2 files changed, 23 insertions(+), 13 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 2dbc0bf..2ea4527 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -123,19 +123,27 @@ struct mca_config {
 };
 
 struct mce_vendor_flags {
-			/*
-			 * overflow recovery cpuid bit indicates that overflow
-			 * conditions are not fatal
-			 */
-	__u64		overflow_recov	: 1,
-
-			/*
-			 * SUCCOR stands for S/W UnCorrectable error COntainment
-			 * and Recovery. It indicates support for data poisoning
-			 * in HW and deferred error interrupts.
-			 */
-			succor		: 1,
-			__reserved_0	: 62;
+	/*
+	 * Indicates that overflow conditions are not fatal, when set.
+	 */
+	__u64 overflow_recov	: 1,
+
+	/*
+	 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
+	 * Recovery. It indicates support for data poisoning in HW and deferred
+	 * error interrupts.
+	 */
+	      succor		: 1,
+
+	/*
+	 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
+	 * the register space for each MCA bank and also increases number of
+	 * banks. Also, to accommodate the new banks and registers, the MCA
+	 * register space is moved to a new MSR range.
+	 */
+	      smca		: 1,
+
+	      __reserved_0	: 61;
 };
 extern struct mce_vendor_flags mce_flags;
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 17b5ec6..3d631c4 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 		mce_amd_feature_init(c);
 		mce_flags.overflow_recov = !!(ebx & BIT(0));
 		mce_flags.succor	 = !!(ebx & BIT(1));
+		mce_flags.smca		 = !!(ebx & BIT(3));
+
 		break;
 		}
 
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