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Message-ID: <DB5PR02MB1141FD51E1411651A7316D74D62C0@DB5PR02MB1141.eurprd02.prod.outlook.com>
Date: Mon, 2 Nov 2015 07:57:43 +0000
From: Noam Camus <noamc@...hip.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
"linux-snps-arc@...ts.infradead.org"
<linux-snps-arc@...ts.infradead.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Tal Zilcer <talz@...hip.com>, Gil Fruchter <gilf@...hip.com>,
Chris Metcalf <cmetcalf@...hip.com>,
Rob Herring <robh+dt@...nel.org>,
John Stultz <john.stultz@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>
Subject: RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver
> From: Daniel Lezcano [mailto:daniel.lezcano@...aro.org]
> Sent: Sunday, November 01, 2015 10:44 PM
> Please add an entry in the clocksource's Kconfig.
> eg:
OK
> Are you sure all the headers are needed ?
Thanks, will revise this part.
> Why do you need to disable the interrupt here ?
Thanks, seem like left over from past issue, I will remove.
> May be you can consider using only the 32bits. Sometimes it is faster than using 64bits arithmetic and reading the register three times.
> https://lkml.org/lkml/2014/6/20/431
Our device can reach 1000MHz.
That means that the 32-bit half of the counter rolls over every ~4 seconds.
I am not sure optimization is justified.
-Noam
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