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Message-ID: <1446542195.23081.5.camel@ellerman.id.au>
Date: Tue, 03 Nov 2015 20:16:35 +1100
From: Michael Ellerman <mpe@...erman.id.au>
To: Anju T <anju@...ux.vnet.ibm.com>, linuxppc-dev@...ts.ozlabs.org,
linux-kernel@...r.kernel.org
Cc: maddy@...ux.vnet.ibm.com, khandual@...ux.vnet.ibm.com,
sukadev@...ux.vnet.ibm.com, acme@...hat.com, dsahern@...il.com,
jolsa@...hat.com, hemant@...ux.vnet.ibm.com,
naveen.n.rao@...ux.vnet.ibm.com
Subject: Re: [PATCH V3 2/3] perf/powerpc :add support for sampling intr
machine state
On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote:
> The perf infrastructure uses a bit mask to find out
> valid registers to display. Define a register mask
> for supported registers defined in asm/perf_regs.h.
> The bit positions also correspond to register IDs
> which is used by perf infrastructure to fetch the register
> values.CONFIG_HAVE_PERF_REGS enables
> sampling of the interrupted machine state.
> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
> new file mode 100644
> index 0000000..0520492
> --- /dev/null
> +++ b/arch/powerpc/perf/perf_regs.c
> @@ -0,0 +1,92 @@
> +#include <linux/errno.h>
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +#include <linux/perf_event.h>
> +#include <linux/bug.h>
> +#include <linux/stddef.h>
> +#include <asm/ptrace.h>
> +#include <asm/perf_regs.h>
> +
> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
> +
> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
> +
> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
<snip>
I realise you're following the example of other architectures, but we have
almost this exact same structure in ptrace.c, see regoffset_table.
It would be really nice if we could share them between ptrace and perf.
cheers
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