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Date:	Tue, 3 Nov 2015 15:39:36 +0100
From:	Tomasz Nowicki <tn@...ihalf.com>
To:	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	Sinan Kaya <okaya@...eaurora.org>
Cc:	bhelgaas@...gle.com, arnd@...db.de, will.deacon@....com,
	catalin.marinas@....com, rjw@...ysocki.net, hanjun.guo@...aro.org,
	jiang.liu@...ux.intel.com, robert.richter@...iumnetworks.com,
	Narinder.Dhillon@...iumnetworks.com, ddaney@...iumnetworks.com,
	Liviu.Dudau@....com, tglx@...utronix.de, wangyijing@...wei.com,
	Suravee.Suthikulpanit@....com, msalter@...hat.com,
	linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-acpi@...r.kernel.org, linux-kernel@...r.kernel.org,
	linaro-acpi@...ts.linaro.org
Subject: Re: [PATCH V1 11/11] arm64, pci, acpi: Support for ACPI based PCI
 hostbridge init

On 03.11.2015 15:15, Lorenzo Pieralisi wrote:
> On Wed, Oct 28, 2015 at 02:46:37PM -0400, Sinan Kaya wrote:
>
> [...]
>
>>> -int raw_pci_write(unsigned int domain, unsigned int bus,
>>> -		unsigned int devfn, int reg, int len, u32 val)
>>> +struct pci_ops pci_root_ops = {
>>> +	.map_bus = pci_mcfg_dev_base,
>>> +	.read = pci_generic_config_read,
>>> +	.write = pci_generic_config_write,
>>
>>
>> Can you change these with pci_generic_config_read32 and
>> pci_generic_config_write32? We have some targets that can only do 32
>> bits PCI config space access.
>
> No.
>
> http://www.spinics.net/lists/linux-pci/msg44869.html
>
> Can you be a bit more specific please ?
>
> Sigh. Looks like we have to start adding platform specific quirks even
> before we merged the generic ACPI PCIe host controller implementation.
>

The sad reality... But my next version will be still generic. Once that 
one appear to be in good shape then we can add quirks.

Regards,
Tomasz
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