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Message-ID: <EE11001F9E5DDD47B7634E2F8A612F2E1629984F@lhreml503-mbs>
Date: Tue, 3 Nov 2015 18:00:10 +0000
From: Gabriele Paoloni <gabriele.paoloni@...wei.com>
To: David Daney <ddaney@...iumnetworks.com>,
Hanjun Guo <hanjun.guo@...aro.org>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Sinan Kaya <okaya@...eaurora.org>,
Tomasz Nowicki <tn@...ihalf.com>,
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Subject: RE: [PATCH V1 11/11] arm64, pci, acpi: Support for ACPI based PCI
hostbridge init
Hi David
> -----Original Message-----
> From: David Daney [mailto:ddaney@...iumnetworks.com]
> Sent: 03 November 2015 17:39
> To: Hanjun Guo
> Cc: Lorenzo Pieralisi; Sinan Kaya; Tomasz Nowicki; bhelgaas@...gle.com;
> arnd@...db.de; will.deacon@....com; catalin.marinas@....com; rjw@...ysocki.net;
> jiang.liu@...ux.intel.com; robert.richter@...iumnetworks.com;
> Narinder.Dhillon@...iumnetworks.com; Liviu.Dudau@....com; tglx@...utronix.de;
> Wangyijing; Suravee.Suthikulpanit@....com; msalter@...hat.com; linux-
> pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> acpi@...r.kernel.org; linux-kernel@...r.kernel.org; Gabriele Paoloni; Wangzhou
> (B); liudongdong (C)
> Subject: Re: [PATCH V1 11/11] arm64, pci, acpi: Support for ACPI based PCI
> hostbridge init
>
> On 11/03/2015 07:19 AM, Hanjun Guo wrote:
> > On 11/03/2015 10:15 PM, Lorenzo Pieralisi wrote:
> >> On Wed, Oct 28, 2015 at 02:46:37PM -0400, Sinan Kaya wrote:
> >>
> >> [...]
> >>
> >>>> -int raw_pci_write(unsigned int domain, unsigned int bus,
> >>>> - unsigned int devfn, int reg, int len, u32 val)
> >>>> +struct pci_ops pci_root_ops = {
> >>>> + .map_bus = pci_mcfg_dev_base,
> >>>> + .read = pci_generic_config_read,
> >>>> + .write = pci_generic_config_write,
> >>>
> >>>
> >>> Can you change these with pci_generic_config_read32 and
> >>> pci_generic_config_write32? We have some targets that can only do 32
> >>> bits PCI config space access.
> >>
> >> No.
> >>
> >> http://www.spinics.net/lists/linux-pci/msg44869.html
> >>
> >> Can you be a bit more specific please ?
> >>
> >> Sigh. Looks like we have to start adding platform specific quirks even
> >> before we merged the generic ACPI PCIe host controller implementation.
> >
> > Cc Gab, Zhou, and Dondong who upstream the hip05 (designware) PCIe host
> > support.
> >
> > I think so, some platform may not support ECAM for root complex,
> > which needs special handling of access config space, we may need
> > to consider those cases.
> >
>
> Yes, it is indeed true. For example, some Cavium ThunderX processors
> fall into this category.
>
> Some options I thought of are:
>
> o Use DECLARE_ACPI_MCFG_FIXUP() in the kernel to supply the needed
> config space accessors.
>
> o Define additional root_device_ids that imply the needed config space
> accessors.
Yes I like this
it would fit designware too
Gab
>
>
> > Thanks
> > Hanjun
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