linux-kernel - [tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems

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Date:	Wed, 4 Nov 2015 03:57:30 -0800
From:	tip-bot for Aravind Gopalakrishnan <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	luto@...nel.org, akpm@...ux-foundation.org, tglx@...utronix.de,
	linux-kernel@...r.kernel.org, Aravind.Gopalakrishnan@....com,
	mingo@...nel.org, bp@...e.de, jacob.w.shin@...il.com,
	ray.huang@....com, hpa@...or.com, fweisbec@...il.com
Subject: [tip:x86/urgent] x86/AMD:
  Fix last level cache topology for AMD Fam17h systems

Commit-ID:  e5e84a26ef2909964d964224b805236293fb4c63
Gitweb:     http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63
Author:     Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Wed, 4 Nov 2015 12:52:06 +0100

x86/AMD: Fix last level cache topology for AMD Fam17h systems

On AMD Fam17h systems, the last level cache is not resident in the
northbridge. Therefore, we cannot assign cpu_llc_id to the same value as
Node ID as we have been doing until now.

We should rather look at the ApicID bits of the core to provide us the
last level cache ID info.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@....com>
Cc: Andrew Morton <akpm@...ux-foundation.org>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Frederic Weisbecker <fweisbec@...il.com>
Cc: "H. Peter Anvin" <hpa@...or.com>
Cc: Huang Rui <ray.huang@....com>
Cc: Ingo Molnar <mingo@...nel.org>
Cc: Jacob Shin <jacob.w.shin@...il.com>
Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com
Signed-off-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..a8816b3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
 	unsigned bits;
 	int cpu = smp_processor_id();
+	unsigned int socket_id, core_complex_id;
 
 	bits = c->x86_coreid_bits;
 	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 	/* use socket ID also for last level cache */
 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 	amd_get_topology(c);
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id	= (c->apicid >> bits) - 1;
+	core_complex_id	= (c->apicid & ((1 << bits) - 1)) >> 3;
+
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }
 
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