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Message-ID: <20151104135451.GB1717@sirena.org.uk>
Date: Wed, 4 Nov 2015 13:54:51 +0000
From: Mark Brown <broonie@...nel.org>
To: Caesar Wang <wxt@...k-chips.com>
Cc: Heiko Stuebner <heiko@...ech.de>,
linux-rockchip@...ts.infradead.org,
Jaroslav Kysela <perex@...ex.cz>, alsa-devel@...a-project.org,
linux-kernel@...r.kernel.org, Takashi Iwai <tiwai@...e.com>,
Liam Girdwood <lgirdwood@...il.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 1/3] ASoC: rockchip: i2s: Add set the divider clock API
On Mon, Nov 02, 2015 at 11:14:00AM +0800, Caesar Wang wrote:
> In order to support more rates, add the divider clock api.
> As the input source clock to the module is MCLK_I2S,
> and by the divider of the module, the clock generator generates
> SCLK and LRCK to transmitter and receiver.
Why is this a requirement? The clock to use as a source should normally
be specified via set_sysclk() and any internal dividers calculated
automatically by the driver.
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