linux-kernel - Re: [PATCH v4 1/3] mtd: arasan: Add device tree binding documentation

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Message-ID: <CAGnW=BZBBwvaCBzqic9R6KA-guFzRSYizNOMTL2+ow-rLkYx2w@mail.gmail.com>
Date:	Fri, 6 Nov 2015 07:59:45 +0530
From:	punnaiah choudary kalluri <punnaia@...inx.com>
To:	Rob Herring <robh@...nel.org>
Cc:	Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@...inx.com>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	David Woodhouse <dwmw2@...radead.org>,
	Brian Norris <computersforpeace@...il.com>,
	"michals@...inx.com" <michals@...inx.com>,
	Kumar Gala <galak@...eaurora.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Punnaiah Choudary <kpc528@...il.com>
Subject: Re: [PATCH v4 1/3] mtd: arasan: Add device tree binding documentation

On Fri, Nov 6, 2015 at 5:19 AM, Rob Herring <robh@...nel.org> wrote:
> On Thu, Nov 05, 2015 at 08:18:42AM +0530, Punnaiah Choudary Kalluri wrote:
>> This patch adds the dts binding document for arasan nand flash
>> controller.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@...inx.com>
>> ---
>> Changes in v4:
>> - Added num-cs property
>> - Added clock support
>> Changes in v3:
>> - None
>> Changes in v2:
>> - None
>> ---
>>  .../devicetree/bindings/mtd/arasan_nfc.txt         | 34 ++++++++++++++++++++++
>>  1 file changed, 34 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/mtd/arasan_nfc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/arasan_nfc.txt b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
>> new file mode 100644
>> index 0000000..02e1ce3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/arasan_nfc.txt
>> @@ -0,0 +1,34 @@
>> +Arasan Nand Flash Controller with ONFI 3.1 support
>> +
>> +Required properties:
>> +- compatible: Should be "arasan,nfc-v3p10"
>
> There should also be a chip specific property. Vendors are known to
> integrate IP blocks in different and interesting ways.

This IP used in xilinx Zynq UltraScale+ MPSoC and we have not observed
any deviations
 to the original IP as of today. We will add chip specific property if
we observe any deviation
to the original IP spec.

Regards,
Punnaiah
>
> Rob
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