linux-kernel - Re: [PATCH v2 04/19] irqchip: add nps Internal and external irqchips

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Message-ID: <alpine.DEB.2.11.1511080051380.4032@nanos>
Date:	Sun, 8 Nov 2015 00:52:33 +0100 (CET)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Noam Camus <noamc@...hip.com>
cc:	"linux-snps-arc@...ts.infradead.org" 
	<linux-snps-arc@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Tal Zilcer <talz@...hip.com>, Gil Fruchter <gilf@...hip.com>,
	Chris Metcalf <cmetcalf@...hip.com>,
	Jason Cooper <jason@...edaemon.net>,
	Marc Zyngier <marc.zyngier@....com>
Subject: Re: [PATCH v2 04/19] irqchip: add nps Internal and external
 irqchips

Noam,

On Sat, 7 Nov 2015, Noam Camus wrote:
> >From: Thomas Gleixner <tglx@...utronix.de>
> >> +     write_aux_reg(AUX_IENABLE, ienb);
> 
> >I can see how that works for per cpu interrupts, but what happens if
> >two cpus run that concurrent for two different interrupts?
> 
> Each CPU got its own HW copy of auxiliary register IENABLE, so
> concurrent access won't be a trouble.

Please put a comment into the code explaining it.

Thanks,

	tglx
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