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Message-ID: <CAKA=qzZNQqzL2sN5WFHog42ak3tsBmj6-Jy=nBoLC8EXn+aOdw@mail.gmail.com>
Date:	Tue, 10 Nov 2015 14:41:59 -0600
From:	Josh Hunt <joshhunt00@...il.com>
To:	Gratian Crisan <gratian.crisan@...com>
Cc:	Peter Zijlstra <peterz@...radead.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	LKML <linux-kernel@...r.kernel.org>,
	Ingo Molnar <mingo@...hat.com>,
	"H . Peter Anvin" <hpa@...or.com>, x86@...nel.org,
	Borislav Petkov <bp@...en8.de>, Josh Cartwright <joshc@...com>,
	gratian@...il.com
Subject: Re: [RFC PATCH] tsc: synchronize TSCs on buggy Intel Xeon E5 CPUs
 with offset error

On Tue, Nov 10, 2015 at 1:47 PM, Gratian Crisan <gratian.crisan@...com> wrote:
>
> The observed behavior does seem to match BT81 errata i.e. the TSC does
> not get reset on warm reboots and it is otherwise stable.
>
If you have a simple testcase to reproduce the problem I'd be
interested in seeing it.

-- 
Josh
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