linux-kernel - Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <alpine.DEB.2.11.1511161610070.3761@nanos>
Date:	Mon, 16 Nov 2015 18:17:09 +0100 (CET)
From:	Thomas Gleixner <tglx@...utronix.de>
To:	Qais Yousef <qais.yousef@...tec.com>
cc:	linux-kernel@...r.kernel.org, jason@...edaemon.net,
	marc.zyngier@....com, jiang.liu@...ux.intel.com,
	ralf@...ux-mips.org, linux-mips@...ux-mips.org
Subject: Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain

On Mon, 9 Nov 2015, Qais Yousef wrote:
> On 11/07/2015 02:51 PM, Thomas Gleixner wrote:
> Generally it's hard to know whether a real device is connected to a hwirq or
> not. I am saving a patch where we get a set of free hwirqs from DT as only the
> SoC designer knows what hwirq are actually free and safe to use for IPI. I'll
> send this patch with the DT IPI changes or the rproc driver that I will be
> send once these changes are merged.
> 
> The current code assumes that the last 2 * NR_CPUs hwirqs are always free to
> use for Linux SMP.

So what you're saying is that you cannot rely on the last X hwirqs
being available for IPIs. That's insane and to my knowledge there is
no hardware out there which does not reserve a consecutive IPI space.

But nevertheless, lets look at the various (possible) requirements we
have:

1) IPI as per_cpu interrupts

   Single hwirq represented by a single irq descriptor

2) IPI with consecutive mapping space

   No extra mapping from virq base to target cpu required as its just
   linear. Everything can be handled via the base virq.

3) IPI with random mapping space

   Seperate mapping virq base to target cpu is required. The obvious
   place to store it are the irq descriptors. That needs a bit
   different machinery for ipi_send_mask(), but it's not rocket
   science.

> > That makes a lot of things simpler. You don't have to keep a mapping
> > of the hwirq to the target cpu. You just can use the base hwirq and
> > calculate the destination hwirq from there when sending an IPI
> > (general Linux ones). The coprocessor one will just be a natural
> > fallout.
> 
> Are you suggesting here to remove the whole new mapping API from the
> generic code or just that it's not necessary to use it in my case?

Err. I'm saying that you did not make use of hierarchical domains. You
just glued the IPI stuff sideways on the GIC.

We certainly want the generic code for managing the allocation etc.

> I'm confused here as well. Is this a complementary API or are you suggesting
> replacing the one this patch introduces?

Those are replacements. We just need to handle the random mapping case
if we really need it.

Thanks,

	tglx
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/