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Message-ID: <CABg9mcvh+SLK-1iF28pCQgXt5WM_H4tH3ntgKSkMHCyMygThgw@mail.gmail.com>
Date: Mon, 16 Nov 2015 20:37:11 -0800
From: Z Lim <zlim.lnx@...il.com>
To: Yang Shi <yang.shi@...aro.org>
Cc: Alexei Starovoitov <ast@...nel.org>,
Daniel Borkmann <daniel@...earbox.net>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will.deacon@....com>,
"David S. Miller" <davem@...emloft.net>,
Xi Wang <xi.wang@...il.com>,
LKML <linux-kernel@...r.kernel.org>,
Network Development <netdev@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
linaro-kernel@...ts.linaro.org
Subject: Re: [PATCH V4 2/2] arm64: bpf: make BPF prologue and epilogue align
with ARM64 AAPCS
On Mon, Nov 16, 2015 at 2:35 PM, Yang Shi <yang.shi@...aro.org> wrote:
> Save and restore FP/LR in BPF prog prologue and epilogue, save SP to FP
> in prologue in order to get the correct stack backtrace.
>
> However, ARM64 JIT used FP (x29) as eBPF fp register, FP is subjected to
> change during function call so it may cause the BPF prog stack base address
> change too.
>
> Use x25 to replace FP as BPF stack base register (fp). Since x25 is callee
> saved register, so it will keep intact during function call.
> It is initialized in BPF prog prologue when BPF prog is started to run
> everytime. Save and restore x25/x26 in BPF prologue and epilogue to keep
> them intact for the outside of BPF. Actually, x26 is unnecessary, but SP
> requires 16 bytes alignment.
>
> So, the BPF stack layout looks like:
>
> high
> original A64_SP => 0:+-----+ BPF prologue
> |FP/LR|
> current A64_FP => -16:+-----+
> | ... | callee saved registers
> +-----+
> | | x25/x26
> BPF fp register => -80:+-----+
> | |
> | ... | BPF prog stack
> | |
> | |
> current A64_SP => +-----+
> | |
> | ... | Function call stack
> | |
> +-----+
> low
>
> CC: Zi Shen Lim <zlim.lnx@...il.com>
> CC: Xi Wang <xi.wang@...il.com>
> Signed-off-by: Yang Shi <yang.shi@...aro.org>
Acked-by: Zi Shen Lim <zlim.lnx@...il.com>
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