linux-kernel - Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20151117092100.76babf7f@arm.com>
Date:	Tue, 17 Nov 2015 09:21:00 +0000
From:	Marc Zyngier <marc.zyngier@....com>
To:	Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Cc:	Ray Jui <rjui@...adcom.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	"galak@...eaurora.org" <galak@...eaurora.org>,
	Michal Simek <michals@...inx.com>,
	Soren Brinkmann <sorenb@...inx.com>,
	"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
	"arnd@...db.de" <arnd@...db.de>,
	"tinamdar@....com" <tinamdar@....com>,
	"treding@...dia.com" <treding@...dia.com>,
	"Minghuan.Lian@...escale.com" <Minghuan.Lian@...escale.com>,
	"m-karicheri2@...com" <m-karicheri2@...com>,
	"hauke@...ke-m.de" <hauke@...ke-m.de>,
	"dhdang@....com" <dhdang@....com>,
	"sbranden@...adcom.com" <sbranden@...adcom.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	Ravikiran Gummaluri <rgummal@...inx.com>
Subject: Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
 PCIe Host Controller

On Tue, 17 Nov 2015 04:59:39 +0000
Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> wrote:

> > On 11/16/2015 7:14 AM, Marc Zyngier wrote:
> > > On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> > >> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> > >>
> > >> Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com>
> > >> Signed-off-by: Ravi Kiran Gummaluri <rgummal@...inx.com>
> > >> ---
> > >> Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc
> > function.
> > >> Moved MSI functionality to separate functions.
> > >> Changed error return values.
> > >> ---
> > >>   .../devicetree/bindings/pci/xilinx-nwl-pcie.txt    |   68 ++
> > >>   drivers/pci/host/Kconfig                           |   16 +-
> > >>   drivers/pci/host/Makefile                          |    1 +
> > >>   drivers/pci/host/pcie-xilinx-nwl.c                 | 1062
> > ++++++++++++++++++++
> > >>   4 files changed, 1144 insertions(+), 3 deletions(-)
> > >>   create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-
> > pcie.txt
> > >>   create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
> > >>
> > >
> > > [...]
> > >
> > >> +static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus
> > >> +*bus) {
> > >> +	struct platform_device *pdev = to_platform_device(pcie->dev);
> > >> +	struct nwl_msi *msi = &pcie->msi;
> > >> +	unsigned long base;
> > >> +	int ret;
> > >> +
> > >> +	mutex_init(&msi->lock);
> > >> +
> > >> +	/* Check for msii_present bit */
> > >> +	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
> > >> +	if (!ret) {
> > >> +		dev_err(pcie->dev, "MSI not present\n");
> > >> +		ret = -EIO;
> > >> +		goto err;
> > >> +	}
> > >> +
> > >> +	/* Enable MSII */
> > >> +	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> > >> +			  MSII_ENABLE, I_MSII_CONTROL);
> > >> +
> > >> +	/* Enable MSII status */
> > >> +	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> > >> +			  MSII_STATUS_ENABLE, I_MSII_CONTROL);
> > >> +
> > >> +	/* setup AFI/FPCI range */
> > >> +	msi->pages = __get_free_pages(GFP_KERNEL, 0);
> > >> +	base = virt_to_phys((void *)msi->pages);
> > >> +	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
> > >> +	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
> > >
> > > BTW, you still haven't answered my question as to why you need to
> > > waste a page of memory here, and why putting a device address doesn't
> > work.
> > >
> > > As this is (to the best of my knowledge) the only driver doing so, I'd
> > > really like you to explain the rational behind this.
> > 
> > Might not be the only driver doing so after I start sending out patches for the
> > iProc MSI support (soon), :)
> > 
> > I'm not sure how it works for the Xilinx NWL controller, which Bharat should
> > be able to help to explain. But for the iProc MSI controller, there's no device
> > I/O memory reserved for MSI posted writes in the ASIC.
> > Therefore one needs to reserve host memory for these writes.
> > >
> 
> Our SoC doesn't reserve any memory for MSI, hence we need to assign a
> memory space for it out of RAM.

Question to both of you: Does the write make it to memory? Or is it
sampled by the bridge and dropped?

What happens if you replace the page in RAM with a dummy address?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/