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Message-ID: <8520D5D51A55D047800579B0941471982585CEB1@XAP-PVEXMBX01.xlnx.xilinx.com>
Date: Wed, 18 Nov 2015 06:51:41 +0000
From: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
To: Ray Jui <rjui@...adcom.com>, Marc Zyngier <marc.zyngier@....com>
CC: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"pawel.moll@....com" <pawel.moll@....com>,
"mark.rutland@....com" <mark.rutland@....com>,
"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
"galak@...eaurora.org" <galak@...eaurora.org>,
Michal Simek <michals@...inx.com>,
Soren Brinkmann <sorenb@...inx.com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"arnd@...db.de" <arnd@...db.de>,
"tinamdar@....com" <tinamdar@....com>,
"treding@...dia.com" <treding@...dia.com>,
"Minghuan.Lian@...escale.com" <Minghuan.Lian@...escale.com>,
"m-karicheri2@...com" <m-karicheri2@...com>,
"hauke@...ke-m.de" <hauke@...ke-m.de>,
"dhdang@....com" <dhdang@....com>,
"sbranden@...adcom.com" <sbranden@...adcom.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
Ravikiran Gummaluri <rgummal@...inx.com>,
"Robin Murphy" <Robin.Murphy@....com>
Subject: RE: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
PCIe Host Controller
> Subject: Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL
> PCIe Host Controller
>
>
>
> On 11/17/2015 5:55 AM, Marc Zyngier wrote:
> > On 17/11/15 13:27, Bharat Kumar Gogada wrote:
> >>>
> >>> On Tue, 17 Nov 2015 04:59:39 +0000
> >>> Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> wrote:
> >>>
> >>>>> On 11/16/2015 7:14 AM, Marc Zyngier wrote:
> >>>>>> On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> >>>>>>> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >>>>>>>
> >>>>>>> Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com>
> >>>>>>> Signed-off-by: Ravi Kiran Gummaluri <rgummal@...inx.com>
> >>>>>>> ---
> >>>>>>> Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc
> >>>>> function.
> >>>>>>> Moved MSI functionality to separate functions.
> >>>>>>> Changed error return values.
> >>>>>>> ---
> >>>>>>> .../devicetree/bindings/pci/xilinx-nwl-pcie.txt | 68 ++
> >>>>>>> drivers/pci/host/Kconfig | 16 +-
> >>>>>>> drivers/pci/host/Makefile | 1 +
> >>>>>>> drivers/pci/host/pcie-xilinx-nwl.c | 1062
> >>>>> ++++++++++++++++++++
> >>>>>>> 4 files changed, 1144 insertions(+), 3 deletions(-)
> >>>>>>> create mode 100644
> >>>>>>> Documentation/devicetree/bindings/pci/xilinx-nwl-
> >>>>> pcie.txt
> >>>>>>> create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
> >>>>>>>
> >>>>>>
> >>>>>> [...]
> >>>>>>
> >>>>>>> +static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct
> >>>>>>> +pci_bus
> >>>>>>> +*bus) {
> >>>>>>> + struct platform_device *pdev = to_platform_device(pcie-
> >>>> dev);
> >>>>>>> + struct nwl_msi *msi = &pcie->msi;
> >>>>>>> + unsigned long base;
> >>>>>>> + int ret;
> >>>>>>> +
> >>>>>>> + mutex_init(&msi->lock);
> >>>>>>> +
> >>>>>>> + /* Check for msii_present bit */
> >>>>>>> + ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) &
> >>> MSII_PRESENT;
> >>>>>>> + if (!ret) {
> >>>>>>> + dev_err(pcie->dev, "MSI not present\n");
> >>>>>>> + ret = -EIO;
> >>>>>>> + goto err;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + /* Enable MSII */
> >>>>>>> + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
> >>> I_MSII_CONTROL) |
> >>>>>>> + MSII_ENABLE, I_MSII_CONTROL);
> >>>>>>> +
> >>>>>>> + /* Enable MSII status */
> >>>>>>> + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,
> >>> I_MSII_CONTROL) |
> >>>>>>> + MSII_STATUS_ENABLE, I_MSII_CONTROL);
> >>>>>>> +
> >>>>>>> + /* setup AFI/FPCI range */
> >>>>>>> + msi->pages = __get_free_pages(GFP_KERNEL, 0);
> >>>>>>> + base = virt_to_phys((void *)msi->pages);
> >>>>>>> + nwl_bridge_writel(pcie, lower_32_bits(base),
> >>> I_MSII_BASE_LO);
> >>>>>>> + nwl_bridge_writel(pcie, upper_32_bits(base),
> >>> I_MSII_BASE_HI);
> >>>>>>
> >>>>>> BTW, you still haven't answered my question as to why you need to
> >>>>>> waste a page of memory here, and why putting a device address
> >>>>>> doesn't
> >>>>> work.
> >>>>>>
> >>>>>> As this is (to the best of my knowledge) the only driver doing
> >>>>>> so, I'd really like you to explain the rational behind this.
> >>>>>
> >>>>> Might not be the only driver doing so after I start sending out
> >>>>> patches for the iProc MSI support (soon), :)
> >>>>>
> >>>>> I'm not sure how it works for the Xilinx NWL controller, which
> >>>>> Bharat should be able to help to explain. But for the iProc MSI
> >>>>> controller, there's no device I/O memory reserved for MSI posted
> >>>>> writes
> >>> in the ASIC.
> >>>>> Therefore one needs to reserve host memory for these writes.
> >>>>>>
> >>>>
> >>>> Our SoC doesn't reserve any memory for MSI, hence we need to assign
> >>>> a memory space for it out of RAM.
> >>>
> >>> Question to both of you: Does the write make it to memory? Or is it
> >>> sampled by the bridge and dropped?
> >>>
> >> No, write will not do any modification in memory, it is consumed by
> bridge.
> >
> > Then you do not need to allocate memory at all. Use whatever memory
> > you already have. CC-ing Robin, as this may have interaction with the
> SMMU.
> >
> >>
Ok, I will try with some random address, without allocating any memory and test it, and will
update accordingly in next patch.
> >>> What happens if you replace the page in RAM with a dummy address?
> >> What do you mean by dummy address ?
> >
> > Any random (and suitably aligned) address. 0x00000deadbeef000 for
> example.
>
> In our case, I'm pretty sure the writes make it to memory (RAM). I can try
> replacing it with a dummy address, but I'm pretty sure that will not work.
>
Thanks,
Bharat
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