linux-kernel - Re: [PATCH v2 19/19] irqchip/mips-gic: Add new DT property to reserve IPIs

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Date:	Wed, 25 Nov 2015 10:09:11 -0600
From:	Rob Herring <robh@...nel.org>
To:	Qais Yousef <qais.yousef@...tec.com>
Cc:	linux-kernel@...r.kernel.org, tglx@...utronix.de,
	jason@...edaemon.net, marc.zyngier@....com,
	jiang.liu@...ux.intel.com, ralf@...ux-mips.org,
	linux-mips@...ux-mips.org, Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH v2 19/19] irqchip/mips-gic: Add new DT property to
 reserve IPIs

On Wed, Nov 25, 2015 at 12:06:57PM +0000, Qais Yousef wrote:
> The new property will allow to specify the range of GIC hwirqs to use for IPIs.
> 
> This is an optinal property. We preserve the previous behaviour of allocating
> the last 2 * gic_vpes if it's not specified or DT is not supported.
> 
> Signed-off-by: Qais Yousef <qais.yousef@...tec.com>
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: Pawel Moll <pawel.moll@....com>
> Cc: Mark Rutland <mark.rutland@....com>
> Cc: Ian Campbell <ijc+devicetree@...lion.org.uk>
> Cc: Kumar Gala <galak@...eaurora.org>
> Cc: devicetree@...r.kernel.org

Acked-by: Rob Herring <robh@...nel.org>

> 
> ---
>  .../devicetree/bindings/interrupt-controller/mips-gic.txt    |  7 +++++++
>  drivers/irqchip/irq-mips-gic.c                               | 12 ++++++++++--
>  2 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> index aae4c384ee1f..173595305e26 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
> @@ -23,6 +23,12 @@ Optional properties:
>  - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
>    to which the GIC may not route interrupts.  Valid values are 2 - 7.
>    This property is ignored if the CPU is started in EIC mode.
> +- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
> +  reserved for IPIs.
> +  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
> +  of the reserved range.
> +  If not specified, the driver will allocate the last 2 * number of VPEs in the
> +  system.
>  
>  Required properties for timer sub-node:
>  - compatible : Should be "mti,gic-timer".
> @@ -44,6 +50,7 @@ Example:
>  		#interrupt-cells = <3>;
>  
>  		mti,reserved-cpu-vectors = <7>;
> +		mti,reserved-ipi-vectors = <40 8>;
>  
>  		timer {
>  			compatible = "mti,gic-timer";
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index c7043a15253b..659fe734d1b7 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -945,6 +945,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
>  			      struct device_node *node)
>  {
>  	unsigned int gicconfig;
> +	unsigned int v[2];
>  
>  	gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
>  
> @@ -1013,8 +1014,15 @@ static void __init __gic_init(unsigned long gic_base_addr,
>  
>  	gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
>  
> -	/* Make the last 2 * NR_CPUS available for IPIs */
> -	bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes);
> +	if (node &&
> +	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", &v, 2)) {
> +		bitmap_set(ipi_resrv, v[0], v[1]);
> +	} else {
> +		/* Make the last 2 * gic_vpes available for IPIs */
> +		bitmap_set(ipi_resrv,
> +			   gic_shared_intrs - 2 * gic_vpes,
> +			   2 * gic_vpes);
> +	}
>  
>  	gic_basic_init();
>  }
> -- 
> 2.1.0
> 
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