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Date: Thu, 26 Nov 2015 05:03:20 +0000 From: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> To: Marc Zyngier <marc.zyngier@....com> CC: "robh+dt@...nel.org" <robh+dt@...nel.org>, "pawel.moll@....com" <pawel.moll@....com>, "mark.rutland@....com" <mark.rutland@....com>, "ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>, "galak@...eaurora.org" <galak@...eaurora.org>, Michal Simek <michals@...inx.com>, Soren Brinkmann <sorenb@...inx.com>, "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "arnd@...db.de" <arnd@...db.de>, "tinamdar@....com" <tinamdar@....com>, "treding@...dia.com" <treding@...dia.com>, "rjui@...adcom.com" <rjui@...adcom.com>, "Minghuan.Lian@...escale.com" <Minghuan.Lian@...escale.com>, "m-karicheri2@...com" <m-karicheri2@...com>, "hauke@...ke-m.de" <hauke@...ke-m.de>, "dhdang@....com" <dhdang@....com>, "sbranden@...adcom.com" <sbranden@...adcom.com>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>, Ravikiran Gummaluri <rgummal@...inx.com> Subject: RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller > Subject: Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL > PCIe Host Controller > > On Wed, 25 Nov 2015 05:40:49 +0000 > Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> wrote: > > > > On Thu, 19 Nov 2015 11:05:23 +0530 > > > Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com> wrote: > > > > > > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@...inx.com> > > > > Signed-off-by: Ravi Kiran Gummaluri <rgummal@...inx.com> > > > > Acked-by: Rob Herring <robh@...nel.org> > > > > --- > > > > + > > > > +#define MSI_ADDRESS 0xDEED0000 > > > > > > How did you pick this value? What if it intersect with some actual RAM? > > > What if a device actually does DMA to that location? > > > > > > Wouldn't it make sense to actually pick a real *device* address (hint: > > > your MSI controller itself) for this purpose, as the device will > > > never DMA there? > > > > > > > > We have already mentioned in previous patch discussion, we don't have > > any device address on our SOC for MSI, that's the reason we are > > allocating a page for MSI in RAM. Since our memory write is consumed > > by bridge and doesn't write to memory, you suggested to use some > > random address, so using some random address. > > This is becoming painful. > > - "write is consumed by bridge and doesn't write to memory": So why are > you using something that has a chance of actually being memory??? Are > you in the business of corrupting unsuspecting data? > > - "we don't have any device address on our SOC for MSI": You have > plenty, and that's the whole of your device space. *All of it*. So > just take the base address of your PCIe controller, and be done with > it. Or your UART. Anything that cannot be DMA'ed to from a PCIe > device, and that is downstream of your PCIe bridge. > Yes, PCIe controller base will be fine, will send next patch addressing this. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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