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Message-ID: <20151201101326.34c11d79@jclayton-pc>
Date: Tue, 1 Dec 2015 10:13:26 -0800
From: Joshua Clayton <stillcompiling@...il.com>
To: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc: Alessandro Zummo <a.zummo@...ertech.it>,
rtc-linux@...glegroups.com, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/9] rtc-pcf2123: Document all registers and useful bits
On Tue, 24 Nov 2015 22:51:36 +0100
Alexandre Belloni <alexandre.belloni@...e-electrons.com> wrote:
> Hi,
>
> On 04/11/2015 at 07:36:32 -0800, Joshua Clayton wrote :
> > Document all 16 registers in the pcf2123, as well as
> > useful bit masks from the Control1 and seconds registers
> >
> > Signed-off-by: Joshua Clayton <stillcompiling@...il.com>
> > ---
> > drivers/rtc/rtc-pcf2123.c | 23 ++++++++++++++++++++++-
> > 1 file changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/rtc/rtc-pcf2123.c b/drivers/rtc/rtc-pcf2123.c
> > index d1953bb..7756210 100644
> > --- a/drivers/rtc/rtc-pcf2123.c
> > +++ b/drivers/rtc/rtc-pcf2123.c
> > @@ -47,6 +47,7 @@
> >
> > #define DRV_VERSION "0.6"
> >
> > +/* REGISTERS */
> > #define PCF2123_REG_CTRL1 (0x00) /* Control Register
> > 1 */ #define PCF2123_REG_CTRL2 (0x01) /* Control
> > Register 2 */ #define PCF2123_REG_SC
> > (0x02) /* datetime */ @@ -56,7 +57,27 @@
> > #define PCF2123_REG_DW (0x06)
> > #define PCF2123_REG_MO (0x07)
> > #define PCF2123_REG_YR (0x08)
> > -
> > +#define PCF2123_REG_ALRM_MN (0x09) /* Alarm
> > Registers */ +#define PCF2123_REG_ALRM_HR (0x0a)
> > +#define PCF2123_REG_ALRM_DM (0x0b)
> > +#define PCF2123_REG_ALRM_DW (0x0c)
> > +#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate
> > Offset Register */ +#define PCF2123_REG_TMR_CLKOUT
> > (0x0e) /* Timer Registers */ +#define
> > PCF2123_REG_CTDWN_TMR (0x0f) +#define
> > PCF2123_REG_MAX (PCF2123_REG_CTDWN_TMR) +
> > +/* PCF2123_REG_CTRL1 BITS */
> > +#define CTRL1_CLEAR (0x00) /* Clear */
> > +#define CTRL1_CORRECTION_INT (0x02) /* Correction
> > Interrupt */ +#define CTRL1_12_HOUR (0x04) /*
> > 12 hour time */ +#define CTRL1_STOP (0x20) /*
> > Stop the clock */ +#define CTRL1_SW_RESET
> > (0x58) /* Software reset */ +#define
> > CTRL1_EXT_TEST (0x80) /* External Clock Test
> > mode */ + +/* PCF2123_REG_SC BITS */
> > +#define OSC_HAS_STOPPED (0x80) /* Clock has
> > been stopped */ +
>
> Can you use the BIT() macro?
>
>
Sure. I Will change that in v2
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