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Message-ID: <565CFC7C.101@gmail.com>
Date:	Mon, 30 Nov 2015 17:48:44 -0800
From:	Florian Fainelli <f.fainelli@...il.com>
To:	Paul Burton <paul.burton@...tec.com>, linux-mips@...ux-mips.org
CC:	Sören Brinkmann <soren.brinkmann@...inx.com>,
	Michal Simek <michal.simek@...inx.com>,
	Jiang Liu <jiang.liu@...ux.intel.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	Rob Herring <robh@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-pci@...r.kernel.org,
	Russell Joyce <russell.joyce@...k.ac.uk>,
	Arnd Bergmann <arnd@...db.de>, linux-kernel@...r.kernel.org,
	Thomas Gleixner <tglx@...utronix.de>,
	Jingoo Han <jingoohan1@...il.com>,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 20/28] net: pch_gbe: clear interrupt FIFO during probe

On 30/11/15 08:21, Paul Burton wrote:
> xilinx_pcie_init_port clears the pending interrupts in the interrupt
> decode register, but does not clear the interrupt FIFO. This would lead
> to spurious interrupts if any were present in the FIFO at probe time.
> Clear the interrupt FIFO prior to the interrupt decode register in order
> to start with a clean slate as expected.
> 
> Signed-off-by: Paul Burton <paul.burton@...tec.com>

Seems like the subject should be "PCI: xilinx: ..." to be consistent
with the changes you are making to this driver earlier in the series?
-- 
Florian
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