Message-ID: <565DFE50.5030708@codeaurora.org>
Date:	Tue, 1 Dec 2015 15:08:48 -0500
From:	Sinan Kaya <okaya@...eaurora.org>
To:	Christopher Covington <cov@...eaurora.org>,
	Bjorn Helgaas <helgaas@...nel.org>,
	Taku Izumi <izumi.taku@...fujitsu.com>
Cc:	linux-pci@...r.kernel.org, timur@...eaurora.org, jcm@...hat.com,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Yijing Wang <wangyijing@...wei.com>,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI/AER: enable SERR# forwarding and role-based error
 reporting

On 12/1/2015 2:21 PM, Christopher Covington wrote:
> On 12/01/2015 01:51 PM, Bjorn Helgaas wrote:
>> [+cc Taku]
> 
> It looks to me like Bjorn intended to add Taku to the distribution list,
> but accidentally left him off, so I'm adding him to the To field in this
> reply.
> 
> Regards,
> Christopher Covington
> 
>> Hi Sinan,
>>
>> On Mon, Oct 26, 2015 at 05:25:02PM -0400, Sinan Kaya wrote:
>>> A PCIe card behind a PCIe switch is unable to report its errors
>>> when SERR# forwarding is not enabled on the PCIe switch's
>>> secondary interface. This is required by the PCIe  spec. 
>>
>> I think enabling SERR# forwarding is only "required by the spec" in
>> the sense that bridges do not forward errors upstream unless the
>> SERR# Enable bit is set, right?  So I would say this is just an
>> ordinary enable bit in the bridge, not a special spec requirement.
>>

Bottom line is that AER errors won't be forwarded if this bit is not set.

>> The Linux AER code doesn't poll for errors; it assumes errors will be
>> propagated upstream to the Root Port, where they will cause an
>> interrupt, so I agree that it doesn't really make sense to enable AER
>> for a device unless we also enable SERR# forwarding in all the bridges
>> leading to it.
>>
>> I assume this patch fixes a problem, e.g., errors reported by a device
>> are not forwarded upstream, so AER never logs them, and with this
>> patch, AER does log them?  

Correct. I'm not observing the AER errors without this patch. After this
patch, I'm seeing the AER errors coming from the endpoints.


>> I suppose we didn't notice this before
>> because some firmware enables SERR# forwarding for us, but yours
>> doesn't?

Possible..., I could have done this in the UEFI BIOS but I'm also
worried about hotplug case. That's why, I chose to submit a patch for
the kernel.

For instance, what happens after hotplug insertion. Will anybody set
these bits? We need some kernel support for some PCIe features to
reconfigure the hardware.

>>
>>> This patch
>>> enables SERR# forwarding and also cleans out compatibility
>>> mode so that AER reporting is enabled.
>>>
>>> Tested with PEX8749-CA RDK.
>>>
>>> Signed-off-by: Sinan Kaya <okaya@...eaurora.org>
>>> ---
>>>  drivers/pci/pcie/aer/aerdrv_core.c | 56 +++++++++++++++++++++++++++++++++++++-
>>>  1 file changed, 55 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
>>> index 9803e3d..acd22d7 100644
>>> --- a/drivers/pci/pcie/aer/aerdrv_core.c
>>> +++ b/drivers/pci/pcie/aer/aerdrv_core.c
>>> @@ -37,21 +37,75 @@ module_param(nosourceid, bool, 0);
>>>  
>>>  int pci_enable_pcie_error_reporting(struct pci_dev *dev)
>>>  {
>>> +	u8 header_type;
>>> +	int pos;
>>> +
>>>  	if (pcie_aer_get_firmware_first(dev))
>>>  		return -EIO;
>>>  
>>> -	if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
>>> +	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
>>> +	if (!pos)
>>>  		return -EIO;
>>>  
>>> +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>>> +
>>> +	/* needs to be a bridge/switch */
>>> +	if (header_type == PCI_HEADER_TYPE_BRIDGE) {
>>> +		u32 status;
>>> +		u16 control;
>>> +
>>> +		/*
>>> +		 * A switch will not forward ERR_ messages coming from an
>>> +		 * endpoint if SERR# forwarding is not enabled.
>>> +		 * AER driver is checking the errors at the root only.
>>> +		 */
>>> +		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
>>> +		control |= PCI_BRIDGE_CTL_SERR;
>>> +		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
>>
>> Does this work for hot-added devices?  I don't see a path that calls
>> pci_enable_pcie_error_reporting() for hot-added devices, so I don't
>> know how the PCI_EXP_AER_FLAGS bits would get set for them.

Yes for me. We remove the root port along with the endpoint during
hotplug. On the next insertion, AER driver get reprobed for the root port.

>> Let's do this in a separate patch.  The SERR# thing is related to
>> propagating error messages upstream.  PCI_ERR_COR_ADV_NFAT is a bit
>> different.
>>
>> I don't understand all the implications of Role-Based Error Reporting.
>> Can you include a pointer to the Linux code that comprehends it?
>> It looks like the section 6.2.7 implementation note is relevant, but I
>> don't understand it yet.

My understanding of the spec is that you can't have AER enabled when
PCI_ERR_COR_ADV_NFAT is 1.

>>
>> Do we need to pay attention to the Role-Based Error Reporting bit in
>> the Device Capabilities register for any reason?  I guess maybe it
>> doesn't matter because Role-Base Error Reporting appeared in PCIe 1.1,
>> and the PCI_ERR_COR_ADV_NFAT bit was reserved prior to that, so it
>> shouldn't do anything if we clear it.
>>
>> Bjorn
>>
>>> +	}
>>> +
>>>  	return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_AER_FLAGS);
>>>  }
>>>  EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
>>>  
>>>  int pci_disable_pcie_error_reporting(struct pci_dev *dev)
>>>  {
>>> +	int pos;
>>> +	u8 header_type;
>>> +
>>>  	if (pcie_aer_get_firmware_first(dev))
>>>  		return -EIO;
>>>  
>>> +	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
>>> +	if (!pos)
>>> +		return -EIO;
>>> +
>>> +	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
>>> +
>>> +	/* needs to be a bridge/switch */
>>> +	if (header_type == PCI_HEADER_TYPE_BRIDGE) {
>>> +		u32 status;
>>> +		u16 control;
>>> +
>>> +		/* clear serr forwarding */
>>> +		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
>>> +		control &= ~PCI_BRIDGE_CTL_SERR;
>>> +		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
>>> +
>>> +		/* set compatibility mode */
>>> +		pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &status);
>>> +		status |= PCI_ERR_COR_ADV_NFAT;
>>> +		pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, status);
>>> +	}
>>> +
>>>  	return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
>>>  					  PCI_EXP_AER_FLAGS);
>>>  }
>>> -- 
>>> Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
>>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>>> the body of a message to majordomo@...r.kernel.org
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> 
> 


-- 
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
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