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Message-ID: <20151203073123.GD14699@codeaurora.org>
Date: Wed, 2 Dec 2015 23:31:23 -0800
From: Stephen Boyd <sboyd@...eaurora.org>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc: Mike Turquette <mturquette@...libre.com>,
Chen-Yu Tsai <wens@...e.org>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v2] clk: sunxi: pll2: Fix clock running too fast
On 12/01, Maxime Ripard wrote:
> Contrary to what the datasheet says, the pre divider doesn't seem to be
> incremented by one in the PLL2, but just uses the value from the register,
> with 0 being a bypass.
>
> This fixes the audio playing too fast.
>
> Since we now have the same pre-divider flags, and the only difference with
> the A10 is the post-divider offset, also remove the structure to just pass
> the offset as an argument.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> ---
Applied to clk-fixes + I added the Fixes tag.
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