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Message-ID: <20151203213812.GA32235@rob-hp-laptop>
Date: Thu, 3 Dec 2015 15:38:12 -0600
From: Rob Herring <robh@...nel.org>
To: Harvey Hunt <harvey.hunt@...tec.com>
Cc: linux-mtd@...ts.infradead.org, Alex Smith <alex.smith@...tec.com>,
Zubair Lutfullah Kakakhel <Zubair.Kakakhel@...tec.com>,
David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v9 1/3] dt-bindings: binding for jz4780-{nand,bch}
On Thu, Dec 03, 2015 at 12:02:20PM +0000, Harvey Hunt wrote:
> From: Alex Smith <alex.smith@...tec.com>
>
> Add DT bindings for NAND devices connected to the NEMC on JZ4780 SoCs,
> as well as the hardware BCH controller, used by the jz4780_{nand,bch}
> drivers.
>
> Signed-off-by: Alex Smith <alex.smith@...tec.com>
> Cc: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@...tec.com>
> Cc: David Woodhouse <dwmw2@...radead.org>
> Cc: Brian Norris <computersforpeace@...il.com>
> Cc: linux-mtd@...ts.infradead.org
> Cc: devicetree@...r.kernel.org
> Cc: linux-kernel@...r.kernel.org
> Signed-off-by: Harvey Hunt <harvey.hunt@...tec.com>
> ---
> v8 -> v9:
> - Document that partitions are represented as a child node of a NAND chip.
Don't multiple flash chips typically get interleaved in order to get
parallelism needed for performance? Then the view of the partitions
would apply across all chips. Anyway, it's optional, so:
Acked-by: Rob Herring <robh@...nel.org>
> v7 -> v8:
> - Describe how NAND chips are now child nodes of the NAND controller.
>
> v6 -> v7:
> - Add nand-ecc-mode to DT bindings.
> - Add nand-on-flash-bbt to DT bindings.
>
> v5 -> v6:
> - No change.
>
> v4 -> v5:
> - Rename ingenic,bch-device to ingenic,bch-controller to fit with
> existing convention.
>
> v3 -> v4:
> - No change
>
> v2 -> v3:
> - Rebase to 4.0-rc6
> - Changed ingenic,ecc-size to common nand-ecc-step-size
> - Changed ingenic,ecc-strength to common nand-ecc-strength
> - Changed ingenic,busy-gpio to common rb-gpios
> - Changed ingenic,wp-gpio to common wp-gpios
>
> v1 -> v2:
> - Rebase to 4.0-rc3
>
> .../bindings/mtd/ingenic,jz4780-nand.txt | 86 ++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> new file mode 100644
> index 0000000..29ea585
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> @@ -0,0 +1,86 @@
> +* Ingenic JZ4780 NAND/BCH
> +
> +This file documents the device tree bindings for NAND flash devices on the
> +JZ4780. NAND devices are connected to the NEMC controller (described in
> +memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
> +be children of the NEMC node.
> +
> +Required NAND controller device properties:
> +- compatible: Should be set to "ingenic,jz4780-nand".
> +- reg: For each bank with a NAND chip attached, should specify a bank number,
> + an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
> +
> +Optional NAND controller device properties:
> +- ingenic,bch-controller: To make use of the hardware BCH controller, this
> + property must contain a phandle for the BCH controller node. The required
> + properties for this node are described below. If this is not specified,
> + software BCH will be used instead.
> +
> +Optional children nodes:
> +- Individual NAND chips are children of the NAND controller node.
> +
> +Required children node properties:
> +- reg: An integer ranging from 1 to 6 representing the CS line to use.
> +
> +Optional children node properties:
> +- nand-ecc-step-size: ECC block size in bytes.
> +- nand-ecc-strength: ECC strength (max number of correctable bits).
> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
> +- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
> +- rb-gpios: GPIO specifier for the busy pin.
> +- wp-gpios: GPIO specifier for the write protect pin.
> +
> +Optional child node of NAND chip nodes:
> +- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
> +
> +Example:
> +
> +nemc: nemc@...10000 {
> + ...
> +
> + nandc: nand-controller@1 {
> + compatible = "ingenic,jz4780-nand";
> + reg = <1 0 0x1000000>; /* Bank 1 */
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ingenic,bch-controller = <&bch>;
> +
> + nand@1 {
> + reg = <1>;
> +
> + nand-ecc-step-size = <1024>;
> + nand-ecc-strength = <24>;
> + nand-ecc-mode = "hw";
> + nand-on-flash-bbt;
> +
> + rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
> +
> + partitions {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ...
> + }
> + };
> + };
> +};
> +
> +The BCH controller is a separate SoC component used for error correction on
> +NAND devices. The following is a description of the device properties for a
> +BCH controller.
> +
> +Required BCH properties:
> +- compatible: Should be set to "ingenic,jz4780-bch".
> +- reg: Should specify the BCH controller registers location and length.
> +- clocks: Clock for the BCH controller.
> +
> +Example:
> +
> +bch: bch@...d0000 {
> + compatible = "ingenic,jz4780-bch";
> + reg = <0x134d0000 0x10000>;
> +
> + clocks = <&cgu JZ4780_CLK_BCH>;
> +};
> --
> 2.6.2
>
> --
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