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Message-ID: <tip-169b932a15318e8e9f2f0f12eeb55dda09c8737f@git.kernel.org>
Date: Sun, 6 Dec 2015 05:16:52 -0800
From: tip-bot for Jiri Olsa <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, eranian@...gle.com, jolsa@...hat.com,
peterz@...radead.org, paulus@...ba.org, jolsa@...nel.org,
tglx@...utronix.de, acme@...hat.com, vincent.weaver@...ne.edu,
torvalds@...ux-foundation.org, mingo@...nel.org, hpa@...or.com
Subject: [tip:perf/core] perf/x86/intel:
Fix INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA macro
Commit-ID: 169b932a15318e8e9f2f0f12eeb55dda09c8737f
Gitweb: http://git.kernel.org/tip/169b932a15318e8e9f2f0f12eeb55dda09c8737f
Author: Jiri Olsa <jolsa@...nel.org>
AuthorDate: Mon, 9 Nov 2015 10:24:31 +0100
Committer: Ingo Molnar <mingo@...nel.org>
CommitDate: Sun, 6 Dec 2015 12:54:48 +0100
perf/x86/intel: Fix INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA macro
We need to add rest of the flags to the constraint mask
instead of another INTEL_ARCH_EVENT_MASK, fixing a typo.
Signed-off-by: Jiri Olsa <jolsa@...nel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Paul Mackerras <paulus@...ba.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Link: http://lkml.kernel.org/r/1447061071-28085-1-git-send-email-jolsa@kernel.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/kernel/cpu/perf_event.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index ab18b8a..d0e35eb 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -387,7 +387,7 @@ struct cpu_hw_events {
/* Check flags and event code/umask, and set the HSW N/A flag */
#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
__EVENT_CONSTRAINT(code, n, \
- INTEL_ARCH_EVENT_MASK|INTEL_ARCH_EVENT_MASK, \
+ INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
--
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