linux-kernel - [PATCH 1/2] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset

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Message-Id: <872e8ef16cfc38e5ff3b45fac1094e6f1722e4ad.1449470704.git.harish.chegondi@intel.com>
Date:	Mon,  7 Dec 2015 14:32:31 -0800
From:	Harish Chegondi <harish.chegondi@...el.com>
To:	linux-kernel@...r.kernel.org, mingo@...hat.com,
	a.p.zijlstra@...llo.nl
Cc:	Harish Chegondi <harish.chegondi@...el.com>,
	Harish Chegondi <harish.chegondi@...il.com>,
	Andi Kleen <andi.kleen@...el.com>,
	Kan Liang <kan.liang@...el.com>,
	Lukasz Anaczkowski <lukasz.anaczkowski@...el.com>
Subject: [PATCH 1/2] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset

Call uncore_pci_box_ctl() function to get the PMON box control MSR offset
instead of hard coding the offset. This would allow us to use this
snbep_uncore_pci_init_box() function for other PCI PMON devices whose box
control MSR offset is different from SNBEP_PCI_PMON_BOX_CTL.

Signed-off-by: Harish Chegondi <harish.chegondi@...el.com>
Cc: Andi Kleen <andi.kleen@...el.com>
Cc: Kan Liang <kan.liang@...el.com>
Cc: Lukasz Anaczkowski <lukasz.anaczkowski@...el.com>
---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index f0f4fcb..2672f51 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -315,8 +315,9 @@ static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct pe
 static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
 {
 	struct pci_dev *pdev = box->pci_dev;
+	int box_ctl = uncore_pci_box_ctl(box);
 
-	pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
+	pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT);
 }
 
 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
-- 
2.1.2.330.g565301e

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