linux-kernel - Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access

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Message-ID: <2295258.Vc5Dp4nsCT@ws-stein>
Date:	Thu, 10 Dec 2015 08:15:14 +0100
From:	Alexander Stein <alexander.stein@...tec-electronic.com>
To:	linux-kernel@...r.kernel.org
Cc:	Bhuvanchandra DV <bhuvanchandra.dv@...adex.com>,
	broonie@...nel.org, stefan@...er.ch, linux-spi@...r.kernel.org
Subject: Re: [PATCH v2] spi-fsl-dspi: Fix CTAR Register access

On Thursday 10 December 2015 11:25:30, Bhuvanchandra DV wrote:
> DSPI instances in Vybrid have a different amount of chip selects
> and CTARs (Clock and transfer Attributes Register). In case of
> DSPI1 we only have 2 CTAR registers and 4 CS. In present driver
> implementation CTAR offset is derived from CS instance which will
> lead to out of bound access if chip select instance is greater than
> CTAR register instance, hence use single CTAR0 register for all CS
> instances. Since we write the CTAR register anyway before each access,
> there is no value in using the additional CTAR registers. Also one
> should not program a value in CTAS for a CTAR register that is not
> present, hence configure CTAS to use CTAR0.

Shouldn't the information put into struct fsl_dspi_devtype_data how much CTAR and CS the actual implementation has available? E.g. LS1021A has 6 CS and 4 CTAR

Best regards,
Alexander
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