linux-kernel - Re: [PATCH 0/4] gpio: pxa: integrate with pincontrol

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Message-ID: <CACRpkdZP=3mDWxoX6PRskztoeow41T9RgDyh82NP1=xnY+S1nQ@mail.gmail.com>
Date:	Thu, 10 Dec 2015 16:02:12 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Robert Jarzmik <robert.jarzmik@...e.fr>
Cc:	Alexandre Courbot <gnurou@...il.com>,
	Haojian Zhuang <haojian.zhuang@...il.com>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Daniel Mack <zonque@...il.com>
Subject: Re: [PATCH 0/4] gpio: pxa: integrate with pincontrol

On Thu, Dec 10, 2015 at 8:28 AM, Robert Jarzmik <robert.jarzmik@...e.fr> wrote:
> Linus Walleij <linus.walleij@...aro.org> writes:
>
>> On Sat, Nov 28, 2015 at 10:37 PM, Robert Jarzmik <robert.jarzmik@...e.fr> wrote:
>>
>>> Hi Linus, Alexandre and Haojian,
>>>
>>> This serie aims at several cleanups and improvements in the pxa gpio driver, to
>>
>> I have concerns about this series.
>>
>> I am worried that joining the banks into one gpio_chip makes it
>> impossible for you GPIOLIB_IRQCHIP. Usually that is possible and
>> preferrable when using a chained handler if e.g. one bank has
>> one IRQ line.
>>
>> But overall that depends on how the IRQs map on this hardware.
>> Can you describe how the GPIO IRQs work on the PXA27x?
> Of course.
>
> For PXA27x, there are 3 interrupts directly connected to the CPU of the SoC,
> ie. the primary irq controller :
>  - one is only triggered if GPIO0 has a rising/falling edge
>  - one is only triggered if GPIO1 has a rising/falling edge
>  - the last is triggered if any GPIOn has a rising/falling edge (n >= 2)
>
> The condition to program the rising/falling edge which implies the interrupt to
> be asserted is in a GPIO block register, GFER and GRER (1 bit per GPIO).
>
> The fact that the last interrupt (let's call it gpiomux_irq) is triggered by
> GPIOs from _all_ the banks makes me believe it's a single IP block, ie. a single
> chip.

OK you're probably right. So GPIO0 and 1 are special cases and the
rest a muxed GPIO case. That's sufficiently odd to warrant its own
irqdomain and not use GPIOLIB_IRQCHIP.

I guess I will go ahead and merge this, simply.

> Now if you have concerns with this, then maybe you can advise another approach,
> I'm pretty open. The final goal will be for me :
>  - gpio and pinctrl have to cooperate
>    - today, with the current state, it's impossible to map pins 0..127 to gpios
>      0..127, at least in a device-tree .dts file

OK sounds good.

>    - the GPDR (gpio direction register) shared access bothers me a bit

How is it shared and between what users?

Yours,
Linus Walleij
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