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Date:	Fri, 11 Dec 2015 10:42:30 +0200
From:	Jarkko Nikula <jarkko.nikula@...ux.intel.com>
To:	Xiangliang Yu <Xiangliang.Yu@....com>,
	andriy.shevchenko@...ux.intel.com, mika.westerberg@...ux.intel.com,
	wsa@...-dreams.de, linux-i2c@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc:	SPG_Linux_Kernel@....com
Subject: Re: [PATCH v2] I2C: designware: fix IO timeout issue for AMD
 controller

On 12/11/2015 02:02 PM, Xiangliang Yu wrote:
> Because of some hardware limitation, AMD I2C controller can't
> trigger pending interrupt if interrupt status has been changed
> after clearing interrupt status bits. Then, I2C will lost
> interrupt and IO timeout.
>
> According to hardware design, this patch implements a workaround
> to disable i2c controller interrupt and re-enable i2c interrupt
> before exiting ISR.
>
> To reduce the performance impacts on other vendors, use unlikely
> function to check flag in ISR.
> ---
> Changes in v2:
>      - pass flags with ->driver_data
>      - unmask interrupt right after masking
>
> Signed-off-by: Xiangliang Yu <Xiangliang.Yu@....com>
> ---
>   drivers/i2c/busses/i2c-designware-core.c    | 6 ++++++
>   drivers/i2c/busses/i2c-designware-core.h    | 1 +
>   drivers/i2c/busses/i2c-designware-platdrv.c | 7 ++++++-
>   3 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
> index 8c48b27..de7fbbb 100644
> --- a/drivers/i2c/busses/i2c-designware-core.c
> +++ b/drivers/i2c/busses/i2c-designware-core.c
> @@ -813,6 +813,12 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
>   tx_aborted:
>   	if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
>   		complete(&dev->cmd_complete);
> +	else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
> +		/* workaround to trigger pending interrupt */
> +		stat = dw_readl(dev, DW_IC_INTR_MASK);
> +		i2c_dw_disable_int(dev);
> +		dw_writel(dev, stat, DW_IC_INTR_MASK);
> +	}
>
Looks ok to me.

Acked-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
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