linux-kernel - [PATCH] sb_edac: Setting fixed DIMM width for Xeon Knights Landing platform.

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Message-Id: <1449840082-18673-1-git-send-email-hubert.chrzaniuk@intel.com>
Date:	Fri, 11 Dec 2015 14:21:22 +0100
From:	Hubert Chrzaniuk <hubert.chrzaniuk@...el.com>
To:	hubert.chrzaniuk@...el.com, lukasz.anaczkowski@...el.com,
	mchehab@....samsung.com, dougthompson@...ssion.com
Cc:	bp@...en8.de, linux-edac@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH] sb_edac: Setting fixed DIMM width for Xeon Knights Landing platform.

Knights Landing does not come with register that could be used
to fetch DIMM width. However the value is fixed for this architecture
so it can be hardcoded.

Fixes: d0cdf900314 (sb_edac: Add Knights Landing (Xeon Phi gen 2) support)
Signed-off-by: Hubert Chrzaniuk <hubert.chrzaniuk@...el.com>
---
 drivers/edac/sb_edac.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
index 9c0424d..6ea9b1f 100644
--- a/drivers/edac/sb_edac.c
+++ b/drivers/edac/sb_edac.c
@@ -924,6 +924,12 @@ out:
 	return mtype;
 }
 
+static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
+{
+	/* for KNL value is fixed */
+	return DEV_X16;
+}
+
 static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
 {
 	/* there's no way to figure out */
@@ -3370,7 +3376,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
 		pvt->info.interleave_list = knl_interleave_list;
 		pvt->info.max_interleave = ARRAY_SIZE(knl_interleave_list);
 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
-		pvt->info.get_width = ibridge_get_width;
+		pvt->info.get_width = knl_get_width;
 		mci->ctl_name = kasprintf(GFP_KERNEL,
 			"Knights Landing Socket#%d", mci->mc_idx);
 
-- 
1.8.3.1

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