lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:	Mon, 14 Dec 2015 12:40:57 +1100
From:	David Gibson <david@...son.dropbear.id.au>
To:	Qais Yousef <qais.yousef@...tec.com>
Cc:	Rob Herring <robh+dt@...nel.org>,
	"devicetree-spec@...r.kernel.org" <devicetree-spec@...r.kernel.org>,
	Jason Cooper <jason@...edaemon.net>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Marc Zyngier <marc.zyngier@....com>,
	Jiang Liu <jiang.liu@...ux.intel.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Lisa Parratt <Lisa.Parratt@...tec.com>
Subject: Re: Generic DT binding for IPIs

On Fri, Dec 11, 2015 at 10:47:57AM +0000, Qais Yousef wrote:
> On 12/11/2015 12:39 AM, David Gibson wrote:
> >On Thu, Dec 10, 2015 at 10:20:49AM +0000, Qais Yousef wrote:
> >>
> >>The IPIs have two properties that are different from a regular interrupts:
> >>
> >>     1. An IPI is not only received, it could also be sent.
> >Any interrupt is sent by the device, received by an interrupt
> >controller, so this isn't really anything fundamentally different.
> 
> No they're not fundamentally different. It's just the way they're created
> and used.
> 
> >>     2. The IPI is dynamic. There's an actual allocation from a pool of
> >>available
> >>         IPIs happening when we ask for one to be reserved.
> >It's not really clear to me what that means, and why it requires any
> >particular different information in the device tree.
> 
> Maybe it would help to look at the new IPI reservation API?
> 
>     https://lkml.org/lkml/2015/12/8/249

Hmm.. not as much as I might have hoped.

From the API, it looks like you're reserving IPIs to signal between
different CPUs all of which are in Linux.  From your description here
it sounds like the coproc is a separate specialized thing not running
Linux (or at least, not the same Linux instance as the host OS which
this device tree is for).

> >>The difference might be borderline..
> >>
> >>Do you have any rough idea on what a possible extension could look like?
> >>Reusing means writing less code, which is always better of course :)
> >>
> >>By the way, on MIPS GIC, we can use interrupts property to describe an IPI
> >>the host system will receive. But to send one to the coprocessor, we need to
> >>define an outgoing IPI.
> >Ah, ok, so is what you're trying to describe here (from the host OS
> >and CPU point of view) a purely outgoing signal to the coproc?
> 
> Yes.

Ok.  In that case 'interrupts' is definitely *not* the right way to
describe this.  'interrupts' describes a signal going _from_ the node
in which it appears, _to_ the (host) cpu.  Or at least to an interrupt
controller which will generally forward it to the host cpu one way or
another.


> >>In this case, the firmware will be hardcoded to send an interrupt to a
> >>specific hwirq, so one can then describe it in DT as a regular interrupt to
> >>the host system. Hardcoding is not ideal and less portable though.
> >Or is the signal that goes to the coproc then somehow being translated
> >into a host interrupt?  If that's so you should be able to represent
> >the coproc as an interrupt controller or interrupt nexus.
> >
> 
> I'm not sure I understood you completely but no, there's no translation
> happening. When the IPI is allocated it would be routed
> to the coproc. When the host wants to send a signal, it'll use the allocated
> hwirq value (indirectly via the virq) to write to a register, which will
> cause an interrupt to be generated at the coproc.

Where is this magic register located?  In the host cpu?  In the
coproc?  In some special IPI controller?

> >>>>      };
> >>>>
> >>>>      coproc2 {
> >>>>              ipi-refs = <&coproc1 "in">, <&coproc1 "coproc2data">, <&coproc1
> >>>>"corpoc2ctrl">;
> >>>This isn't actually parseable. You need a known length of cells after a phandle.
> >>>
> >>To clarify, what you're saying we can't pass strings, right?
> >So, I'm not entirely sure what point Rob was making.  The above
> >certainly isn't valid dts syntax - strings can't appear within
> >the < > construct.  But if you make the obvious fix to:
> >     ipi-refs = <&coproc1>, "in", <&coproc1>, "coproc2data";
> >
> >then it's certainly a parseable property format.  It's kind of clunky
> >mixing integers and strings that way, but it's possible and there are
> >existing bindings using properties in a similar format.
> >
> 
> Ah OK thanks! I think this form would be handy to get the refs even if we
> end up reusing the interrupts property to allocate an IPI.
> 
> So if reusing the interrupts property is the right thing to do, do you (or
> anyone else) have a rough idea how this should look like?

So as noted above, I'm now sure that 'interrupts' is not the right
thing.  I'm trying to understand the coprocs and the ipi mechanism a
bit better to work out if there is something existing which would make
sense, or if we do need something entirely new.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Download attachment "signature.asc" of type "application/pgp-signature" (820 bytes)

Powered by blists - more mailing lists