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Message-id: <1393132421.659011450082398931.JavaMail.weblogic@epmlwas07b>
Date:	Mon, 14 Dec 2015 08:40:03 +0000 (GMT)
From:	MyungJoo Ham <myungjoo.ham@...sung.com>
To:	최찬우 <cw00.choi@...sung.com>,
	크쉬시토프 
	<k.kozlowski@...sung.com>, "kgene@...nel.org" <kgene@...nel.org>
Cc:	박경민 <kyungmin.park@...sung.com>,
	"robh+dt@...nel.org" <robh+dt@...nel.org>,
	"pawel.moll@....com" <pawel.moll@....com>,
	"mark.rutland@....com" <mark.rutland@....com>,
	"ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>,
	"galak@...eaurora.org" <galak@...eaurora.org>,
	"linux@....linux.org.uk" <linux@....linux.org.uk>,
	"tjakobi@...h.uni-bielefeld.de" <tjakobi@...h.uni-bielefeld.de>,
	"linux.amoon@...il.com" <linux.amoon@...il.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-pm@...r.kernel.org" <linux-pm@...r.kernel.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH v4 02/20] PM / devfreq: exynos: Add documentation for
 generic exynos bus frequency driver

>   
>  This patch adds the documentation for generic exynos bus frequency
> driver.
> 
> Signed-off-by: Chanwoo Choi <cw00.choi@...sung.com>
> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@...sung.com>

A little changes following:

> ---
>  .../devicetree/bindings/devfreq/exynos-bus.txt     | 93 ++++++++++++++++++++++
>  1 file changed, 93 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> new file mode 100644
> index 000000000000..e32daef328da
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
> @@ -0,0 +1,93 @@
> +* Generic Exynos Bus frequency device
> +
> +The Samsung Exynos SoC have many buses for data transfer between DRAM

+The Samsung Exynos SoC has many buses for data transfer between DRAM

or

+The Samsung Exynos SoCs have many buses for data transfer between DRAM
(because you intend to support mulitple Exynos SoCs)

> +and sub-blocks in SoC. Almost Exynos SoC have the common architecture

+and sub-blocks in SoC. Most Exynos SoCs share the common architecture

> +for buses. Generally, the each bus of Exynos SoC includes the source clock

+for buses. Generally, each bus of Exynos SoC includes a source clock

> +and power line and then is able to change the clock according to the usage

+and a power line, which are able to change the clock frequency 

> +of each buses on runtime. When gathering the usage of each buses on runtime,

+of the bus in runtime. To monitor the usage of each bus in runtime,

> +the driver uses the PPMU (Platform Performance Monitoring Unit) which

+the driver uses the PPMU (Platform Performance Monitoring Unit), which

> +is able to measure the current load of sub-blocks.
> +
> +There are a little different composition among Exynos SoC because each Exynos
> +SoC has the different sub-blocks. So, this difference should be specified

+SoC has different sub-blocks. Therefore, such difference should be specified

> +in devicetree file instead of each device driver. In result, this driver
> +is able to support the bus frequency for all Exynos SoCs.
> +
[]

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