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Message-ID: <20151214123957.GF11630@pd.tnic>
Date: Mon, 14 Dec 2015 13:39:57 +0100
From: Borislav Petkov <bp@...e.de>
To: Will Deacon <will.deacon@....com>
Cc: Mark Rutland <mark.rutland@....com>,
Linaro ACPI Mailman List <linaro-acpi@...ts.linaro.org>,
Catalin Marinas <catalin.marinas@....com>,
rruigrok@...eaurora.org, Michal Hocko <mhocko@...e.cz>,
Fu Wei <fu.wei@...aro.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Al Stone <al.stone@...aro.org>,
Tomasz Nowicki <tn@...ihalf.com>,
"Abdulhamid, Harb" <harba@....qualcomm.com>,
linux-acpi@...r.kernel.org, Vlastimil Babka <vbabka@...e.cz>,
Mark Salter <msalter@...hat.com>,
Grant Likely <grant.likely@...aro.org>,
Len Brown <lenb@...nel.org>,
Marc Zyngier <Marc.Zyngier@....com>,
Jon Masters <jcm@...hat.com>,
Tomasz Nowicki <tomasz.nowicki@...aro.org>,
rrichter@...ium.com, linux-arm-kernel@...ts.infradead.org,
G Gregory <graeme.gregory@...aro.org>,
Rafael Wysocki <rjw@...ysocki.net>,
LKML <linux-kernel@...r.kernel.org>,
jarkko.nikula@...ux.intel.com, Hanjun Guo <hanjun.guo@...aro.org>,
Jonathan Zhang <jon.zhixiong.zhang@...il.com>,
Tony Luck <tony.luck@...el.com>
Subject: Re: [PATCH v4] acpi, apei, arm64: APEI initial support for aarch64.
On Mon, Dec 14, 2015 at 11:46:59AM +0000, Will Deacon wrote:
> We're in violent agreement. I'm just saying that's *why*
> arch_apei_flush_tlb_one exists, as opposed to calling unmap_kernel_range
> in the driver (which will attempt IPIs). On arm64, unmap_kernel_range
> will actually work correctly, since we don't need IPIs to broadcast TLB
> maintenance.
>
> The (incorrect) premise earlier in the thread was that
> arch_apei_flush_tlb_one exists because there's no portable API for
> flushing a single page, but that's simply not true.
Right.
> Yikes, I'd not even thought about that. Perhaps its all serialised
> somehow, but I have no idea.
Yeah, didn't see any serialization there...
> Right, imagine the following sequence of events:
>
> 1. CPU x takes a GHES IRQ
> 2. CPU x then maps the buffer a page at a time in ghes_copy_tofrom_phys.
> After each unmap, it performs a local TLBI. Let's say that it has
> the final page of the buffer mapped when...
> 3. ... CPU y is meanwhile happily executing some other kernel code.
> 4. CPU y's page table walker speculatively fills the TLB with a translation
> for the last buffer page that CPU x has mapped (because its just been
> mapped with ioremap_page_range and is in the kernel page table).
> 5. CPU x unmaps the last page, performs a *local* TLBI, handles the
> event and returns from the exception
> 6. CPU y takes a GHES IRQ
> 7. CPU y then maps the first buffer page at the same virtual address
> that CPU x used to map the last buffer page
> 8. CPU y accesses the page, hits the stale TLB entry and gets junk
>
> which I think means you need to perform local TLB invalidation on map
> as well as unmap.
>
> Is there some reason this can't happen on x86? It sounds plausible on
> arm64 if we were to use local invalidation.
Ha, thanks for the detailed example, I see it now!
And I too don't see a reason why that can't happen. And the GHES
IRQ is a GSI, which has "global" in the name but I don't think that
means it interrupts the whole system like an NMI does. Especially
if it is registered/handled like a normal irq: acpi_gsi_to_irq() ..
request_irq()...
Adding Tony.
If anything, we probably should be doing something with irq_work at the
end of ghes_copy_tofrom_phys() so that the invalidation of any possible
speculative mappings happens before we return from the GHES IRQ.
Hmm, currently I'm not even clear whether this'll work: we would
theoretically need to send IPIs from IRQ context, at the end of the GHES
IRQ...
Thanks.
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
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