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Message-Id: <20151215112711.94D37140B04@ozlabs.org>
Date: Tue, 15 Dec 2015 22:27:11 +1100 (AEDT)
From: Michael Ellerman <mpe@...erman.id.au>
To: Boqun Feng <boqun.feng@...il.com>, linux-kernel@...r.kernel.org,
linuxppc-dev@...ts.ozlabs.org
Cc: Peter Zijlstra <peterz@...radead.org>,
Boqun Feng <boqun.feng@...il.com>,
Will Deacon <will.deacon@....com>, stable@...r.kernel.org,
Paul Mackerras <paulus@...ba.org>,
Thomas Gleixner <tglx@...utronix.de>,
"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
Ingo Molnar <mingo@...nel.org>
Subject: Re: [powerpc/next, 2/2] powerpc: Make {cmp}xchg* and their atomic_ versions fully ordered
On Mon, 2015-02-11 at 01:30:32 UTC, Boqun Feng wrote:
> According to memory-barriers.txt, xchg*, cmpxchg* and their atomic_
> versions all need to be fully ordered, however they are now just
> RELEASE+ACQUIRE, which are not fully ordered.
>
> So also replace PPC_RELEASE_BARRIER and PPC_ACQUIRE_BARRIER with
> PPC_ATOMIC_ENTRY_BARRIER and PPC_ATOMIC_EXIT_BARRIER in
> __{cmp,}xchg_{u32,u64} respectively to guarantee fully ordered semantics
> of atomic{,64}_{cmp,}xchg() and {cmp,}xchg(), as a complement of commit
> b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
>
> This patch depends on patch "powerpc: Make value-returning atomics fully
> ordered" for PPC_ATOMIC_ENTRY_BARRIER definition.
>
> Cc: <stable@...r.kernel.org> # 3.4+
> Signed-off-by: Boqun Feng <boqun.feng@...il.com>
> Reviewed-by: Paul E. McKenney <paulmck@...ux.vnet.ibm.com>
> Acked-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/81d7a3294de7e9828310bbf9
cheers
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