linux-kernel - Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology Support

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Message-ID: <alpine.DEB.2.20.1512181141190.4547@east.gentwo.org>
Date:	Fri, 18 Dec 2015 11:45:29 -0600 (CST)
From:	Christoph Lameter <cl@...ux.com>
To:	Fenghua Yu <fenghua.yu@...el.com>
cc:	"H. Peter Anvin" <hpa@...ux.intel.com>,
	Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>,
	Tony Luck <tony.luck@...el.com>,
	Ravi V Shankar <ravi.v.shankar@...el.com>,
	Peter Zijlstra <peterz@...radead.org>,
	Tejun Heo <tj@...nel.org>,
	Marcelo Tosatti <mtosatti@...hat.com>,
	linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>
Subject: Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology
 Support

On Thu, 17 Dec 2015, Fenghua Yu wrote:

> 	Intel Cache allocation support:
>
> 	Cache allocation patches adds a cgroup subsystem to support the new
> Cache Allocation feature found in future Intel Xeon Intel processors.
> Cache Allocation is a sub-feature with in Resource Director
> Technology(RDT) feature. Current patches support only L3 cache
> allocation.
>
> Cache Allocation provides a way for the Software (OS/VMM) to restrict
> cache allocation to a defined 'subset' of cache which may be overlapping
> with other 'subsets'.  This feature is used when a thread is allocating
> a cache line ie when pulling new data into the cache.
>
> Threads are associated with a CLOS(Class of service). OS specifies the
> CLOS of a thread by writing the IA32_PQR_ASSOC MSR during context
> switch. The cache capacity associated with CLOS 'n' is specified by
> writing to the IA32_L3_MASK_n MSR.

Could you also support another low level interface where a task (or
process) can set the CLOS id itself if it has CAP_SYS_NICE. Plus some way
for the supervisor to directly control the IA32_L3_MASK_n MSR?

Is there a way to see these values for debugging purposes?

We tightly control processes and bind them to processors. cpusets are
often a too high level instrument at that level.

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