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Message-ID: <20151221105545.51688120@redhat.com>
Date:	Mon, 21 Dec 2015 10:55:45 -0500
From:	Luiz Capitulino <lcapitulino@...hat.com>
To:	"Fenghua Yu" <fenghua.yu@...el.com>
Cc:	"H. Peter Anvin" <hpa@...ux.intel.com>,
	"Ingo Molnar" <mingo@...e.hu>,
	"Thomas Gleixner" <tglx@...utronix.de>,
	"Tony Luck" <tony.luck@...el.com>,
	"Ravi V Shankar" <ravi.v.shankar@...el.com>,
	"Peter Zijlstra" <peterz@...radead.org>,
	"Tejun Heo" <tj@...nel.org>,
	"Marcelo Tosatti" <mtosatti@...hat.com>,
	"linux-kernel" <linux-kernel@...r.kernel.org>,
	"x86" <x86@...nel.org>
Subject: Re: [PATCH V16 00/11] x86: Intel Cache Allocation Technology
 Support

On Thu, 17 Dec 2015 14:46:05 -0800
"Fenghua Yu" <fenghua.yu@...el.com> wrote:

> Changes in V16:
>  - Port to latest upstream kernel
>  - Add a spin lock to handle contention when writing closid to MSR and
>    creating closid by a user.

Fenghua, Peter, what about all the discussion v15 got
about this interface being just wrong? Where's that
addressed?

 - https://lkml.org/lkml/2015/11/18/637

 - http://lkml.iu.edu/hypermail/linux/kernel/1511.0/02375.html
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