From c824845238f0e027d480bfc3b9ad482ae901b78b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 4 Jun 2012 10:14:50 +0300 Subject: [PATCH v2] dw_dmac: debug dma controller IO Signed-off-by: Andy Shevchenko --- drivers/dma/dw/core.c | 8 +++++--- drivers/dma/dw/regs.h | 26 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c index dcf19f0..d50c39c 100644 --- a/drivers/dma/dw/core.c +++ b/drivers/dma/dw/core.c @@ -570,9 +570,10 @@ static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, if (dwc->mask) { void (*callback)(void *param); void *callback_param; + dma_addr_t llp = channel_readl(dwc, LLP); - dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", - channel_readl(dwc, LLP)); + dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp %pad\n", + &llp); callback = dwc->cdesc->period_callback; callback_param = dwc->cdesc->period_callback_param; @@ -1571,6 +1572,8 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) pm_runtime_get_sync(chip->dev); + dw->dma.dev = chip->dev; + dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); autocfg = dw_params >> DW_PARAMS_EN & 0x1; @@ -1715,7 +1718,6 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); if (pdata->is_private) dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); - dw->dma.dev = chip->dev; dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; dw->dma.device_free_chan_resources = dwc_free_chan_resources; diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h index 3a3a5e1..a3b881c 100644 --- a/drivers/dma/dw/regs.h +++ b/drivers/dma/dw/regs.h @@ -130,6 +130,8 @@ struct dw_dma_regs { #define dma_writel_native writel #endif +#define DW_DMAC_IO_DEBUG + /* To access the registers in early stage of probe */ #define dma_read_byaddr(addr, name) \ dma_readl_native((addr) + offsetof(struct dw_dma_regs, name)) @@ -301,10 +303,22 @@ __dwc_regs(struct dw_dma_chan *dwc) return dwc->ch_regs; } +#ifdef DW_DMAC_IO_DEBUG +#define channel_readl(dwc, name) ({ \ + unsigned int val = dma_readl_native(&(__dwc_regs(dwc)->name)); \ + dev_dbg(chan2dev(&dwc->chan), "readl: " #name " 0x%08x\n", (u32)val); \ + val; \ +}) +#define channel_writel(dwc, name, val) ({ \ + dev_dbg(chan2dev(&dwc->chan), "writel: " #name " 0x%08x\n", (u32)val); \ + dma_writel_native((val), &(__dwc_regs(dwc)->name)); \ +}) +#else #define channel_readl(dwc, name) \ dma_readl_native(&(__dwc_regs(dwc)->name)) #define channel_writel(dwc, name, val) \ dma_writel_native((val), &(__dwc_regs(dwc)->name)) +#endif static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) { @@ -333,10 +347,22 @@ static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) return dw->regs; } +#ifdef DW_DMAC_IO_DEBUG +#define dma_readl(dw, name) ({ \ + unsigned int val = dma_readl_native(&(__dw_regs(dw)->name)); \ + dev_dbg(dw->dma.dev, "readl: " #name " 0x%08x\n", (u32)val); \ + val; \ +}) +#define dma_writel(dw, name, val) ({ \ + dev_dbg(dw->dma.dev, "writel: " #name " 0x%08x\n", (u32)val); \ + dma_writel_native((val), &(__dw_regs(dw)->name)); \ +}) +#else #define dma_readl(dw, name) \ dma_readl_native(&(__dw_regs(dw)->name)) #define dma_writel(dw, name, val) \ dma_writel_native((val), &(__dw_regs(dw)->name)) +#endif #define channel_set_bit(dw, reg, mask) \ dma_writel(dw, reg, ((mask) << 8) | (mask)) -- 2.1.3