linux-kernel - Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel

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Message-ID: <yw1xr3if4n74.fsf@unicorn.mansr.com>
Date:	Mon, 21 Dec 2015 19:27:11 +0000
From:	Måns Rullgård <mans@...sr.com>
To:	Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc:	Andy Shevchenko <andy.shevchenko@...il.com>,
	Julian Margetson <runaway@...dw.ms>, Tejun Heo <tj@...nel.org>,
	linux-ide@...r.kernel.org,
	"linux-kernel\@vger.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/3] ata: sata_dwc_460ex: use "dmas" DT property to find dma channel

Andy Shevchenko <andriy.shevchenko@...ux.intel.com> writes:

> On Mon, 2015-12-21 at 01:19 +0000, Måns Rullgård wrote:
>> Andy Shevchenko <andy.shevchenko@...il.com> writes:
>> 
>> > P.S. I also noticed that original driver enables interrupt per each
>> > block
>> 
>> And then ignores all but the transfer complete interrupt.
>> 
>> > and sets protection control bits.
>> 
>> With no indication what the value it sets is supposed to mean.
>
> Okay, let's summarize what we have:
>
> 0. AR: Get a working reference for PPC 460EX SATA driver

Do we consider Julian's latest result working?

> 1. AR: Clear LLP_EN bits at the last block of LLP transfer

Patch sent.

> 2. AR: Rename masters to 'memory' and 'peripheral' and change them per
> DMA direction

Good idea.  I'd call them memory and device though to match existing
dmaengine nomenclature.

> 3. AR: Set LMS (LLP master) to 'memory' when do LLP transfers

I started working on a patch for that already.

> 4. CHECK: PROTCTL bit (documentation says that recommended value is
> 0x01)

Any idea what the value of 0x3 used by the old sata driver means?
Presumably that's decided by the bus.

> 5. CHECK: Other bits in CFG register (FIFO_MODE, FCMODE)
> 6. CHECK: Block interrupts vs. one interrupt at the end of block chain
> (Måns, I missed how any of them is ignored)

The interrupt handler looks at the StatusTfr and StatusErr registers and
ignores StatusBlock.

> 7. AR: Test everything on Intel SoCs such as Baytrail, CherryTrail, etc
> (SPI, UART, dmatest), AVR32 (MMC, dmatest), PPC 460EX (Onboard SATA)

I can test on AVR32.  That is as far as I know the only system I have
with this DMA engine.

> I can share my working branch with a set of patches regarding to
> dw_dmac. We may do our work based on that code and after I'll submit
> everything to upstream. Does it sound okay for you, guys?

I'm going away for the holidays, so I won't be able to do any serious
work on this until January, but I'll keep an eye on emails and may even
reply occasionally.  Before I go, I'll publish my patches so far
whatever shape they're in.

-- 
Måns Rullgård
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