linux-kernel - [PATCH v1 3/3] ARM64 LPC: update binding doc

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Message-Id: <1451396032-23708-4-git-send-email-zourongrong@gmail.com>
Date:	Tue, 29 Dec 2015 21:33:52 +0800
From:	Rongrong Zou <zourongrong@...il.com>
To:	arnd@...db.de, catalin.marinas@....com, will.deacon@....com
Cc:	benh@...nel.crashing.org, lijianhua@...wei.com,
	lixiancai@...wei.com, linuxarm@...wei.com,
	linux-kernel@...r.kernel.org, minyard@....org,
	gregkh@...uxfoundation.org
Subject: [PATCH v1 3/3] ARM64 LPC: update binding doc

Signed-off-by: Rongrong Zou <zourongrong@...il.com>
---
 .../devicetree/bindings/arm64/low-pin-count.txt      | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm64/low-pin-count.txt

diff --git a/Documentation/devicetree/bindings/arm64/low-pin-count.txt b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
new file mode 100644
index 0000000..215f2c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm64/low-pin-count.txt
@@ -0,0 +1,20 @@
+Low Pin Count bus driver
+
+Usually LPC controller is part of PCI host bridge, so the legacy ISA
+port locate on LPC bus can be accessed directly. But some SoC have
+independent LPC controller, and we can access the legacy port by specifying
+LPC address cycle. Thus, LPC driver is introduced.
+
+Required properties:
+- compatible: "low-pin-count"
+- reg: specifies low pin count address range
+
+
+Example:
+
+        lpc_0: lpc@...b0000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+                compatible = "low-pin-count";
+                reg = <0x0 0xa01b0000 0x0 0x10000>;
+        };
-- 
1.9.1

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