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Message-ID: <201512301527.FKQcF5Zx%fengguang.wu@intel.com>
Date: Wed, 30 Dec 2015 15:13:20 +0800
From: kbuild test robot <lkp@...el.com>
To: Jiancheng Xue <xuejiancheng@...wei.com>
Cc: kbuild-all@...org, robh+dt@...nel.org, pawel.moll@....com,
mark.rutland@....com, ijc+devicetree@...lion.org.uk,
galak@...eaurora.org, dwmw2@...radead.org,
computersforpeace@...il.com, shijie.huang@...el.com,
pengbinquan@...wei.com, xuejiancheng@...wei.com,
han.xu@...escale.com, ezequiel@...guardiasur.com.ar,
fabio.estevam@...escale.com, manabian@...il.com,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mtd@...ts.infradead.org, yanhaifeng@...ilicon.com,
yanghongwei@...ilicon.com, suwenping@...ilicon.com,
ml.yang@...ilicon.com, gaofei@...ilicon.com,
zhangzhenxing@...ilicon.com, xuejiancheng@...ilicon.com
Subject: Re: [PATCH] mtd: spi-nor: add hisilicon spi-nor flash controller
driver
Hi Jiancheng,
[auto build test WARNING on v4.4-rc7]
[cannot apply to next-20151223]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]
url: https://github.com/0day-ci/linux/commits/Jiancheng-Xue/mtd-spi-nor-add-hisilicon-spi-nor-flash-controller-driver/20151230-104117
config: arm64-allmodconfig (attached as .config)
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All warnings (new ones prefixed by >>):
drivers/mtd/spi-nor/hisi-sfc.c: In function 'hisi_spi_nor_send_cmd':
>> drivers/mtd/spi-nor/hisi-sfc.c:239:9: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
reg = (u32)buf;
^
drivers/mtd/spi-nor/hisi-sfc.c: In function 'hisi_spi_nor_erase':
>> drivers/mtd/spi-nor/hisi-sfc.c:376:6: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
(u8 *)(u32)offs, 0);
^
vim +239 drivers/mtd/spi-nor/hisi-sfc.c
233 hisi_spi_nor_cmd_prepare(host, cmd, buf, &op_cfg);
234
235 reg = FMC_CMD_CMD1(cmd);
236 writel(reg, host->regbase + FMC_CMD);
237
238 if (op_cfg & FMC_OP_ADDR_EN) {
> 239 reg = (u32)buf;
240 writel(reg, host->regbase + FMC_ADDRL);
241 }
242
243 reg = OP_CFG_FM_CS(priv->chipselect);
244 if (op_cfg & FMC_OP_ADDR_EN)
245 reg |= OP_CFG_ADDR_NUM(nor->addr_width);
246 writel(reg, host->regbase + FMC_OP_CFG);
247
248 reg = FMC_DATA_NUM_CNT(len);
249 writel(reg, host->regbase + FMC_DATA_NUM);
250
251 writel(0xff, host->regbase + FMC_INT_CLR);
252 reg = op_cfg | FMC_OP_REG_OP_START;
253 writel(reg, host->regbase + FMC_OP);
254 wait_op_finish(host);
255
256 return 0;
257 }
258
259 static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
260 int len)
261 {
262 struct hifmc_priv *priv = nor->priv;
263 struct hifmc_host *host = priv->host;
264 int ret;
265
266 ret = hisi_spi_nor_send_cmd(nor, opcode, buf, len);
267 if (ret)
268 return ret;
269
270 memcpy(buf, host->iobase, len);
271
272 return ret;
273 }
274
275 static int hisi_spi_nor_write_reg(struct spi_nor *nor, u8 opcode,
276 u8 *buf, int len)
277 {
278 struct hifmc_priv *priv = nor->priv;
279 struct hifmc_host *host = priv->host;
280
281 if (len)
282 memcpy(host->iobase, buf, len);
283
284 return hisi_spi_nor_send_cmd(nor, opcode, buf, len);
285 }
286
287 static void hisi_spi_nor_dma_transfer(struct spi_nor *nor, u32 start_off,
288 u32 dma_buf, u32 len, u8 op_type)
289 {
290 struct hifmc_priv *priv = nor->priv;
291 struct hifmc_host *host = priv->host;
292 u8 if_type = 0, dummy = 0;
293 u8 w_cmd = 0, r_cmd = 0;
294 u32 reg;
295
296 writel(start_off, host->regbase + FMC_ADDRL);
297
298 if (op_type == FMC_OP_READ) {
299 if_type = get_if_type(nor->flash_read);
300 dummy = nor->read_dummy >> 3;
301 r_cmd = nor->read_opcode;
302 } else
303 w_cmd = nor->program_opcode;
304
305 reg = OP_CFG_FM_CS(priv->chipselect)
306 | OP_CFG_MEM_IF_TYPE(if_type)
307 | OP_CFG_ADDR_NUM(nor->addr_width)
308 | OP_CFG_DUMMY_NUM(dummy);
309 writel(reg, host->regbase + FMC_OP_CFG);
310
311 reg = FMC_DMA_LEN_SET(len);
312 writel(reg, host->regbase + FMC_DMA_LEN);
313 writel(dma_buf, host->regbase + FMC_DMA_SADDR_D0);
314
315 reg = OP_CTRL_RD_OPCODE(r_cmd)
316 | OP_CTRL_WR_OPCODE(w_cmd)
317 | OP_CTRL_RW_OP(op_type)
318 | OP_CTRL_DMA_OP_READY;
319 writel(0xff, host->regbase + FMC_INT_CLR);
320 writel(reg, host->regbase + FMC_OP_DMA);
321 wait_op_finish(host);
322 }
323
324 static int hisi_spi_nor_read(struct spi_nor *nor, loff_t from, size_t len,
325 size_t *retlen, u_char *read_buf)
326 {
327 struct hifmc_priv *priv = nor->priv;
328 struct hifmc_host *host = priv->host;
329 unsigned char *ptr = read_buf;
330 int num;
331
332 while (len > 0) {
333 num = (len >= HIFMC_DMA_MAX_LEN)
334 ? HIFMC_DMA_MAX_LEN : len;
335 hisi_spi_nor_dma_transfer(nor, from, host->dma_buffer,
336 num, FMC_OP_READ);
337 memcpy(ptr, host->buffer, num);
338 ptr += num;
339 from += num;
340 len -= num;
341 }
342 *retlen += (size_t)(ptr - read_buf);
343
344 return 0;
345 }
346
347 static void hisi_spi_nor_write(struct spi_nor *nor, loff_t to,
348 size_t len, size_t *retlen, const u_char *write_buf)
349 {
350 struct hifmc_priv *priv = nor->priv;
351 struct hifmc_host *host = priv->host;
352 const unsigned char *ptr = write_buf;
353 int num;
354
355 while (len > 0) {
356 if (to & HIFMC_DMA_MASK)
357 num = (HIFMC_DMA_MAX_LEN - (to & HIFMC_DMA_MASK))
358 >= len ? len
359 : (HIFMC_DMA_MAX_LEN - (to & HIFMC_DMA_MASK));
360 else
361 num = (len >= HIFMC_DMA_MAX_LEN)
362 ? HIFMC_DMA_MAX_LEN : len;
363 memcpy(host->buffer, ptr, num);
364 hisi_spi_nor_dma_transfer(nor, to, host->dma_buffer, num,
365 FMC_OP_WRITE);
366 to += num;
367 ptr += num;
368 len -= num;
369 }
370 *retlen += (size_t)(ptr - write_buf);
371 }
372
373 static int hisi_spi_nor_erase(struct spi_nor *nor, loff_t offs)
374 {
375 return hisi_spi_nor_send_cmd(nor, nor->erase_opcode,
> 376 (u8 *)(u32)offs, 0);
377 }
378
379 static int hisi_spi_nor_probe(struct platform_device *pdev)
---
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