linux-kernel - [tip:perf/core] perf/x86: Allow zero PEBS status with only single active event

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Message-ID: <tip-01330d7288e0050c5aaabc558059ff91589e67cd@git.kernel.org>
Date:	Wed, 6 Jan 2016 10:50:50 -0800
From:	tip-bot for Andi Kleen <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	tglx@...utronix.de, mingo@...nel.org, jolsa@...hat.com,
	acme@...hat.com, hpa@...or.com, vincent.weaver@...ne.edu,
	peterz@...radead.org, eranian@...gle.com,
	torvalds@...ux-foundation.org, linux-kernel@...r.kernel.org,
	ak@...ux.intel.com
Subject: [tip:perf/core] perf/x86:
  Allow zero PEBS status with only single active event

Commit-ID:  01330d7288e0050c5aaabc558059ff91589e67cd
Gitweb:     http://git.kernel.org/tip/01330d7288e0050c5aaabc558059ff91589e67cd
Author:     Andi Kleen <ak@...ux.intel.com>
AuthorDate: Thu, 3 Dec 2015 13:22:20 -0800
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 6 Jan 2016 11:15:31 +0100

perf/x86: Allow zero PEBS status with only single active event

Normally we drop PEBS events with a zero status field. But when
there is only a single PEBS event active we can assume the
PEBS record is for that event. The PEBS buffer is always flushed
when PEBS events are disabled, so there is no risk of mishandling
state PEBS records this way.

Signed-off-by: Andi Kleen <ak@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Link: http://lkml.kernel.org/r/1449177740-5422-2-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_ds.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 0e3a9c7..cd1993e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -1230,6 +1230,18 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
 		pebs_status = p->status & cpuc->pebs_enabled;
 		pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
 
+		/*
+		 * On some CPUs the PEBS status can be zero when PEBS is
+		 * racing with clearing of GLOBAL_STATUS.
+		 *
+		 * Normally we would drop that record, but in the
+		 * case when there is only a single active PEBS event
+		 * we can assume it's for that event.
+		 */
+		if (!pebs_status && cpuc->pebs_enabled &&
+			!(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
+			pebs_status = cpuc->pebs_enabled;
+
 		bit = find_first_bit((unsigned long *)&pebs_status,
 					x86_pmu.max_pebs_events);
 		if (bit >= x86_pmu.max_pebs_events)
--
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