linux-kernel - [tip:perf/core] perf/x86: fix PEBS issues on Intel Atom/Core2

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Message-ID: <tip-1424a09a9e1839285e948d4ea9fdfca26c9a2086@git.kernel.org>
Date:	Wed, 6 Jan 2016 10:52:24 -0800
From:	tip-bot for Stephane Eranian <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, eranian@...gle.com, mingo@...nel.org,
	vincent.weaver@...ne.edu, jolsa@...hat.com,
	torvalds@...ux-foundation.org, hpa@...or.com, acme@...hat.com,
	peterz@...radead.org, tglx@...utronix.de
Subject: [tip:perf/core] perf/x86: fix PEBS issues on Intel Atom/Core2

Commit-ID:  1424a09a9e1839285e948d4ea9fdfca26c9a2086
Gitweb:     http://git.kernel.org/tip/1424a09a9e1839285e948d4ea9fdfca26c9a2086
Author:     Stephane Eranian <eranian@...gle.com>
AuthorDate: Thu, 3 Dec 2015 23:33:18 +0100
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Wed, 6 Jan 2016 11:15:34 +0100

perf/x86: fix PEBS issues on Intel Atom/Core2

This patch fixes broken PEBS support on Intel Atom and Core2
due to wrong pointer arithmetic in intel_pmu_drain_pebs_core().

The get_next_pebs_record_by_bit() was called on PEBS format fmt0
which does not use the pebs_record_nhm layout.

Signed-off-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Cc: kan.liang@...el.com
Fixes: 21509084f999 ("perf/x86/intel: Handle multiple records in the PEBS buffer")
Link: http://lkml.kernel.org/r/1449182000-31524-3-git-send-email-eranian@google.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_ds.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 9c0f8d4..a7463ed 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -1106,6 +1106,13 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
 	void *at;
 	u64 pebs_status;
 
+	/*
+	 * fmt0 does not have a status bitfield (does not use
+	 * perf_record_nhm format)
+	 */
+	if (x86_pmu.intel_cap.pebs_format < 1)
+		return base;
+
 	if (base == NULL)
 		return NULL;
 
@@ -1191,7 +1198,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 	if (!event->attr.precise_ip)
 		return;
 
-	n = (top - at) / x86_pmu.pebs_record_size;
+	n = top - at;
 	if (n <= 0)
 		return;
 
--
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