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Message-ID: <CA+55aFxChuKFYyUtG6a+zn82JFB=9XaM6mH9V+kdYa9iEDKUzQ@mail.gmail.com>
Date: Fri, 8 Jan 2016 15:41:10 -0800
From: Linus Torvalds <torvalds@...ux-foundation.org>
To: Andy Lutomirski <luto@...nel.org>
Cc: "the arch/x86 maintainers" <x86@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Borislav Petkov <bp@...en8.de>,
Brian Gerst <brgerst@...il.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Oleg Nesterov <oleg@...hat.com>,
"linux-mm@...ck.org" <linux-mm@...ck.org>
Subject: Re: [RFC 09/13] x86/mm: Disable interrupts when flushing the TLB
using CR3
On Fri, Jan 8, 2016 at 3:15 PM, Andy Lutomirski <luto@...nel.org> wrote:
> + /*
> + * We mustn't be preempted or handle an IPI while reading and
> + * writing CR3. Preemption could switch mms and switch back, and
> + * an IPI could call leave_mm. Either of those could cause our
> + * PCID to change asynchronously.
> + */
> + raw_local_irq_save(flags);
> native_write_cr3(native_read_cr3());
> + raw_local_irq_restore(flags);
This seems sad for two reasons:
- it adds unnecessary overhead on non-pcid setups (32-bit being an
example of that)
- on pcid setups, wouldn't invpcid_flush_single_context() be better?
So on the whole I hate it.
Why isn't this something like
if (static_cpu_has_safe(X86_FEATURE_INVPCID)) {
invpcid_flush_single_context();
return;
}
native_write_cr3(native_read_cr3());
*without* any flag saving crud?
And yes, that means that we'd require X86_FEATURE_INVPCID in order to
use X86_FEATURE_PCID, but that seems fine.
Or is there some reason you wanted the odd flags version? If so, that
should be documented.
Linus
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