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Date:	Fri, 8 Jan 2016 15:19:35 +0000
From:	Mark Rutland <mark.rutland@....com>
To:	John Garry <john.garry@...wei.com>
Cc:	JBottomley@...n.com, martin.petersen@...cle.com,
	robh+dt@...nel.org, pawel.moll@....com,
	ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
	linuxarm@...wei.com, zhangfei.gao@...aro.org, xuwei5@...ilicon.com,
	john.garry2@...l.dcu.ie, linux-scsi@...r.kernel.org,
	linux-kernel@...r.kernel.org, arnd@...db.de,
	devicetree@...r.kernel.org
Subject: Re: [PATCH 01/23] devicetree: bindings: hisi_sas: add v2 HW bindings

> >>@@ -25,11 +26,28 @@ Main node required properties:
> >>  		The phy interrupts are ordered into groups of 3 per phy
> >>  		(broadcast, phyup, and abnormal) in increasing order.
> >>  		Completion queue interrupts : each completion queue has 1
> >>-			interrupt source.
> >>-			The interrupts are ordered in increasing order.
> >>+			interrupt source. The interrupts are ordered in
> >>+			increasing order.
> >>  		Fatal interrupts : the fatal interrupts are ordered as follows:
> >>  			- ECC
> >>  			- AXI bus
> >>+		For v2 hw: Interrupts for phys, Sata, and completion queues;
> >>+		the interrupts are ordered in 3 groups, as follows:
> >>+		  - Phy interrupts
> >>+		  - Sata interrupts
> >>+		  - Completion queue interrupts
> >>+		Phy interrupts : Each controller has 2 phy interrupts:
> >>+			- phy up/down
> >>+			- channel interrupt
> >>+		Sata interrupts : Each phy on the controller has 1 Sata
> >>+			interrupt. The interrupts are ordered in increasing
> >>+			order.
> >>+		Completion queue interrupts : each completion queue has 1
> >>+			interrupt source. The interrupts are ordered in
> >>+			increasing order.
> >
> >There are no fatal interrupts in V2?
> 
> For v2 hardware, broadcast and fatal interrupts are mutliplexed into
> the general purpose channel interrupt line.

Ok, that sounds fine, just thought I should check.

> >>+Optional main node properties:
> >>+ - am-max-trans : limit controller for am max transmissions
> >
> >Is this a boolean? Number?
> >
> 
> This is a boolean. It is for dealing with a quirk in the chipset: an
> instance of the controller in the hip06 chipset requires registers
> set with a different init value.

Ok. I think the property at needs a better description for that.

It's not clear to me how "limit controller for am max transmissions"
maps to writing a specific value to some registers, but I don't know
much about SAS.

Is this some well-known thing, or values specific to hip06?

Thanks,
Mark.

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