linux-kernel - [tip:x86/mm] x86/mm: Micro-optimise clflush_cache

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Date:	Fri, 8 Jan 2016 10:30:53 -0800
From:	tip-bot for Chris Wilson <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	tglx@...utronix.de, ross.zwisler@...ux.intel.com, mcgrof@...e.com,
	chris@...is-wilson.co.uk, bp@...e.de, hpa@...or.com,
	linux-kernel@...r.kernel.org, mingo@...nel.org,
	sfr@...b.auug.org.au, sai.praneeth.prakhya@...el.com,
	toshi.kani@....com
Subject: [tip:x86/mm] x86/mm: Micro-optimise clflush_cache_range()

Commit-ID:  1f1a89ac05f6e88aa341e86e57435fdbb1177c0c
Gitweb:     http://git.kernel.org/tip/1f1a89ac05f6e88aa341e86e57435fdbb1177c0c
Author:     Chris Wilson <chris@...is-wilson.co.uk>
AuthorDate: Fri, 8 Jan 2016 09:55:33 +0000
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 8 Jan 2016 19:27:39 +0100

x86/mm: Micro-optimise clflush_cache_range()

Whilst inspecting the asm for clflush_cache_range() and some perf profiles
that required extensive flushing of single cachelines (from part of the
intel-gpu-tools GPU benchmarks), we noticed that gcc was reloading
boot_cpu_data.x86_clflush_size on every iteration of the loop. We can
manually hoist that read which perf regarded as taking ~25% of the
function time for a single cacheline flush.

Signed-off-by: Chris Wilson <chris@...is-wilson.co.uk>
Reviewed-by: Ross Zwisler <ross.zwisler@...ux.intel.com>
Acked-by: "H. Peter Anvin" <hpa@...or.com>
Cc: Toshi Kani <toshi.kani@....com>
Cc: Borislav Petkov <bp@...e.de>
Cc: Luis R. Rodriguez <mcgrof@...e.com>
Cc: Stephen Rothwell <sfr@...b.auug.org.au>
Cc: Sai Praneeth <sai.praneeth.prakhya@...el.com>
Link: http://lkml.kernel.org/r/1452246933-10890-1-git-send-email-chris@chris-wilson.co.uk
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 arch/x86/mm/pageattr.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index a3137a4..6000ad7 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -129,14 +129,16 @@ within(unsigned long addr, unsigned long start, unsigned long end)
  */
 void clflush_cache_range(void *vaddr, unsigned int size)
 {
-	unsigned long clflush_mask = boot_cpu_data.x86_clflush_size - 1;
+	const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
+	void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
 	void *vend = vaddr + size;
-	void *p;
+
+	if (p >= vend)
+		return;
 
 	mb();
 
-	for (p = (void *)((unsigned long)vaddr & ~clflush_mask);
-	     p < vend; p += boot_cpu_data.x86_clflush_size)
+	for (; p < vend; p += clflush_size)
 		clflushopt(p);
 
 	mb();