linux-kernel - Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per bank

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <569825B6.6020507@amd.com>
Date:	Thu, 14 Jan 2016 16:48:22 -0600
From:	Aravind Gopalakrishnan <aravind.gopalakrishnan@....com>
To:	Borislav Petkov <bp@...en8.de>
CC:	<tony.luck@...el.com>, <tglx@...utronix.de>, <mingo@...hat.com>,
	<hpa@...or.com>, <x86@...nel.org>, <linux-edac@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/5] x86/mcheck/AMD: Reduce number of blocks scanned per
 bank

On 1/14/2016 4:37 PM, Borislav Petkov wrote:
> On Thu, Jan 14, 2016 at 04:05:38PM -0600, Aravind Gopalakrishnan wrote:
>>   
>> -#define NR_BLOCKS         9
>> +#define NR_BLOCKS         5
> This doesn't look necessary to me. We do check MCi_MISC[BlkPtr] before
> accessing that MSR.
>

True. But that BlkPtr logic also will undergo changes as it's 
interpretation for future processors is different.

We are guaranteed to have all the MISC registers (all 5 of them) going 
forward.
But we shouldn't be accessing MSRs beyond the 5th extended MISC register 
for each bank as that is the architectural boundary.
Hence the change here.

Thanks,
-Aravind.